/*---------------------------------------------------------------------------*/
PROCESS_THREAD(interrupt_sample_process, ev, data)
{
/* Any process must start with this. */
PROCESS_BEGIN();
interrupt_init(1, 1, 1, 1);
interrupt_enable(INT0);
interrupt_enable(INT1);
/* Register current process with INT0 & INT1*/
interrupt_register(INT0);
interrupt_register(INT1);
while(1) {
/* Wait for an event. */
PROCESS_WAIT_EVENT();
/* Got the interrupt event~ */
if (ev == PROCESS_EVENT_INTERRUPT) {
/* Check for the int_vect. */
if (INT0 == ((struct interrupt *)data)->int_vect) {
/* Got an INT0 interrupt. */
leds_toggle(LEDS_RED);
}
else if (INT1 == ((struct interrupt *)data)->int_vect) {
/* Got an INT1 interrupt. */
leds_toggle(LEDS_YELLOW);
interrupt_disable(INT0);
}
}
} // while (1)
/* Any process must end with this, even if it is never reached. */
PROCESS_END();
}
/**
* Initialize disk device driver. Reserves memory for data structures
* and register driver to the interrupt handler.
*
* @param desc Pointer to the YAMS IO device descriptor of the disk
*
* @return Pointer to the device structure of the disk
*/
device_t *disk_init(io_descriptor_t *desc) {
device_t *dev;
gbd_t *gbd;
disk_real_device_t *real_dev;
uint32_t irq_mask;
dev = (device_t*)stalloc(sizeof(device_t));
gbd = (gbd_t*)stalloc(sizeof(gbd_t));
real_dev = (disk_real_device_t*)stalloc(sizeof(disk_real_device_t));
if (dev == NULL || gbd == NULL || real_dev == NULL)
KERNEL_PANIC("Could not allocate memory for disk driver.");
dev->generic_device = gbd;
dev->real_device = real_dev;
dev->descriptor = desc;
dev->io_address = desc->io_area_base;
dev->type = desc->type;
gbd->device = dev;
gbd->read_block = disk_read_block;
gbd->write_block = disk_write_block;
gbd->block_size = disk_block_size;
gbd->total_blocks = disk_total_blocks;
spinlock_reset(&real_dev->slock);
real_dev->request_queue = NULL;
real_dev->request_served = NULL;
irq_mask = 1 << (desc->irq + 10);
interrupt_register(irq_mask, disk_interrupt_handle, dev);
return dev;
}
int main()
{
uint8_t mac[6];
uint32_t timer = 0;
/* Obtain the ethernet MAC address */
eth_mac(mac);
const char *ipaddr="192.168.0.150";
uint16_t port_be = 0;
interrupt_register(irq_timer, GUEST_TIMER_INT);
/* Configure the virtual ethernet driver */
struct pico_device* eth_dev = PICO_ZALLOC(sizeof(struct pico_device));
if(!eth_dev) {
return 0;
}
eth_dev->send = eth_send;
eth_dev->poll = eth_poll;
eth_dev->link_state = eth_link_state;
if( 0 != pico_device_init((struct pico_device *)eth_dev, "virt-eth", mac)) {
printf ("\nDevice init failed.");
PICO_FREE(eth_dev);
return 0;
}
/* picoTCP initialization */
printf("\nInitializing pico stack\n");
pico_stack_init();
wolfSSL_Debugging_ON();
pico_string_to_ipv4(ipaddr, &my_eth_addr.addr);
pico_string_to_ipv4("255.255.255.0", &netmask.addr);
pico_ipv4_link_add(eth_dev, my_eth_addr, netmask);
port_be = short_be(LISTENING_PORT);
/* WolfSSL initialization only, to make sure libwolfssl.a is needed */
pico_https_setCertificate(cert_pem_2048, sizeof(cert_pem_2048));
pico_https_setPrivateKey(privkey_pem_2048, sizeof(privkey_pem_2048));
pico_https_server_start(0, serverWakeup);
while (1){
eth_watchdog(&timer, 500);
/* pooling picoTCP stack */
pico_stack_tick();
}
return 0;
}
void arch_timer_init(uint32_t frequency)
{
int div = 1193180 / frequency;
outb(PIT_CMD, 0x36);
outb(PIT0_DATA, div & 0xFF);
outb(PIT0_DATA, div >> 8);
extern void timer_intr(registers_t *);
interrupt_register(IRQ0, &timer_intr);
}
/**
* Initializes interrupt driven tty driver. Memory is reserved for
* data structures and tty interrupt handler is registerded.
*
* @param desc Pointer to a YAMS device descriptor data structure.
*
* @return Pointer to tty's device_t structure.
*/
device_t *tty_init(io_descriptor_t *desc) {
device_t *dev;
gcd_t *gcd;
tty_real_device_t *tty_rd;
uint32_t irq_mask;
static int num_of_inits = 0;
dev = (device_t*)stalloc(sizeof(device_t));
if(dev == NULL)
KERNEL_PANIC("Could not reserve memory for tty driver.");
gcd = (gcd_t*)stalloc(sizeof(gcd_t));
if(gcd == NULL)
KERNEL_PANIC("Could not reserve memory for tty driver.");
dev->generic_device = gcd;
dev->io_address = desc->io_area_base;
dev->type = desc->type;
gcd->device = dev;
gcd->write = tty_write;
gcd->read = tty_read;
tty_rd = (tty_real_device_t*)stalloc(sizeof(tty_real_device_t));
if(tty_rd == NULL)
KERNEL_PANIC("Could not reserve memory for tty driver.");
dev->real_device = tty_rd;
if (num_of_inits == 0) {
/* First tty driver will share the device with the polling TTY.
* That is, we use the same spinlock with it. (The spinlock is
* kprintf's because that is the only proper way to access the
* polling tty.) */
tty_rd->slock = &kprintf_slock;
} else {
tty_rd->slock = (spinlock_t*)stalloc(sizeof(spinlock_t));
if(tty_rd->slock == NULL)
KERNEL_PANIC("Could not reserve memory for tty driver spinlock.");
spinlock_reset(tty_rd->slock);
}
num_of_inits++;
tty_rd->write_head = 0;
tty_rd->write_count = 0;
tty_rd->read_head = 0;
tty_rd->read_count = 0;
irq_mask = 1 << (desc->irq + 10);
interrupt_register(irq_mask, tty_interrupt_handle, dev);
return dev;
}
int i386_pc_timer_initialize(void)
{
int err;
pit_initialize();
err = interrupt_register(PIC_IRQ_PIT, INTERRUPT_CALLBACK, timer_handler);
if (err < 0) {
console_message(T_ERR, "Unable to register timer handler");
return err;
}
return 0;
}
void PIT::Initialize(int frequency, InterruptHandler callback)
{
interrupt_register(PIC_IRQ_OFFSET, callback);
uint32_t divisor = (frequency > 0) ? PIT_FREQUENCY / frequency : 0;
// Valid range for divisor is 16 bits (0 is interpreted as 65536)
if (divisor > 0xFFFF) divisor = 0; // Cap at 18.2 Hz
else if (divisor < 1) divisor = 1; // Cap at 1193182 Hz
io_out_8(PIT_COMMAND, PIT_INIT_TIMER);
io_out_8(PIT_CHANNEL0, divisor & 0xFF);
io_out_8(PIT_CHANNEL0, divisor >> 8);
// TODO: ugly!
g_interruptController->Enable(0);
}
//---------------------------------------------------------------------
// Main Entry Point for the master core
//---------------------------------------------------------------------
int master_main()
{
//ToDo: Necessary ??? (See below ...)
Init_QMSS_CPPI();
Init_IPC();
//Register PCIe IRQ
interrupt_register();
// Initialization finished
logout("Ready to receive PCIe commands ...\n\n");
// Process HPRPC requests coming in over PCIe (never returns)
hprpc_serve_irqs();
return 0;
}
/** Initializes a CPU status device. These devices are currently used
* for detecting the total number of CPUs in the system. In addition
* to this a mechanism for generating interrupts on the CPU is
* supported.
*
* @param desc Pointer to the YAMS IO device descriptor of the CPU
* status device
*
* @return Pointer to the device structure of the CPU status device
*/
device_t *cpustatus_init(io_descriptor_t *desc)
{
device_t *dev;
cpu_real_device_t *cpu;
uint32_t irq_mask;
dev = fill_device_t(desc, NULL);
cpu = kmalloc(sizeof(cpu_real_device_t));
if (cpu == NULL)
KERNEL_PANIC("Could not reserve memory for CPU status device driver.");
spinlock_reset(&cpu->slock);
dev->real_device = cpu;
irq_mask = 1 << (desc->irq + 10);
interrupt_register(irq_mask, cpustatus_interrupt_handle, dev);
return dev;
}
/**
* Initialize disk device driver. Reserves memory for data structures
* and register driver to the interrupt handler.
*
* @param desc Pointer to the PCI IO device descriptor of the controller
*
* @return Pointer to the device structure of the controller
*/
int disk_init(io_descriptor_t *desc)
{
/* Cast it */
pci_conf_t *pci = (pci_conf_t*)(uint64_t*) desc;
/* Set bases to default values */
uint16_t iobase1 = IDE_PRIMARY_CMD_BASE;
uint16_t iobase2 = IDE_SECONDARY_CMD_BASE;
uint16_t ctrlbase1 = IDE_PRIMARY_CTRL_BASE;
uint16_t ctrlbase2 = IDE_SECONDARY_CTRL_BASE;
uint16_t busmaster = pci->bar4;
uint32_t i, j, count = 0;
uint16_t buf[256];
/* Check for compatability mode */
if(pci->prog_if & 0x1)
{
/* Native mode for channel 1 */
iobase1 = (uint16_t)pci->bar0;
ctrlbase1 = (uint16_t)pci->bar1;
/* Check if they can be relocated */
if(iobase1 & 0x1)
iobase1--;
if(ctrlbase1 & 0x1)
ctrlbase1--;
}
if(pci->prog_if & 0x4)
{
/* Native mode for channel 2 */
iobase2 = (uint16_t)pci->bar2;
ctrlbase2 = (uint16_t)pci->bar3;
/* Check if they can be relocated */
if(iobase2 & 0x1)
iobase2--;
if(ctrlbase2 & 0x1)
ctrlbase2--;
}
/* Setup Channels */
ide_channels[IDE_PRIMARY].busm = busmaster;
ide_channels[IDE_PRIMARY].base = iobase1;
ide_channels[IDE_PRIMARY].ctrl = ctrlbase1;
ide_channels[IDE_PRIMARY].irq = IDE_PRIMARY_IRQ;
ide_channels[IDE_PRIMARY].irq_wait = 0;
ide_channels[IDE_PRIMARY].dma_phys = 0;
ide_channels[IDE_PRIMARY].dma_virt = 0;
ide_channels[IDE_PRIMARY].dma_buf_phys = 0;
ide_channels[IDE_PRIMARY].dma_buf_virt = 0;
ide_channels[IDE_SECONDARY].busm = busmaster;
ide_channels[IDE_SECONDARY].base = iobase2;
ide_channels[IDE_SECONDARY].ctrl = ctrlbase2;
ide_channels[IDE_SECONDARY].irq = IDE_SECONDARY_IRQ;
ide_channels[IDE_SECONDARY].irq_wait = 0;
ide_channels[IDE_SECONDARY].dma_phys = 0;
ide_channels[IDE_SECONDARY].dma_virt = 0;
ide_channels[IDE_SECONDARY].dma_buf_phys = 0;
ide_channels[IDE_SECONDARY].dma_buf_virt = 0;
/* Install interrupts */
interrupt_register(IDE_PRIMARY_IRQ, (int_handler_t)ide_irq_handler0, 0);
interrupt_register(IDE_SECONDARY_IRQ, (int_handler_t)ide_irq_handler1, 0);
/* Disable Irqs, we use polling mode */
ide_write(IDE_PRIMARY, IDE_REGISTER_CTRL, 2);
ide_write(IDE_SECONDARY, IDE_REGISTER_CTRL, 2);
/* Enumerate devices */
/* We send an IDE_IDENTIFY command to each device, on
* each channel, and see if it responds */
for(i = 0; i < IDE_CHANNELS_PER_CTRL; i++)
{
for(j = 0; j < IDE_DEVICES_PER_CHANNEL; j++)
{
/* Variables */
uint8_t error = 0, type = 0, status = 0;
uint32_t lba28 = 0;
uint64_t lba48 = 0;
ide_devices[count].present = 0; //assume no drive
/* Step 1. Select drive */
ide_write(i, IDE_REGISTER_HDDSEL, 0xA0 | (j << 4));
ide_delay(i);
/* Step 2. Send IDE_IDENTIFY */
ide_write(i, IDE_REGISTER_SECCOUNT0, 0);
ide_write(i, IDE_REGISTER_LBA0, 0);
ide_write(i, IDE_REGISTER_LBA1, 0);
ide_write(i, IDE_REGISTER_LBA2, 0);
ide_write(i, IDE_REGISTER_LBA2, 0);
ide_write(i, IDE_REGISTER_COMMAND, IDE_COMMAND_IDENTIFY);
ide_delay(i);
/* Step 3. Poll */
status = _inb(ide_channels[i].base + IDE_REGISTER_STATUS);
if(status == 0 || status == 0x7F || status == 0xFF)
{
count++;
continue;
}
/* Wuhuu! device is here */
while(1)
{
status = _inb(ide_channels[i].base + IDE_REGISTER_STATUS);
if(status & 0x1)
{
error = 1;
break;
}
if(!(status & IDE_ATA_BUSY) && (status & IDE_ATA_DRQ))
{
break;
}
}
/* Step 4. Probe for ATAPI */
if(error != 0)
{
/* Get type */
uint8_t cl = _inb(ide_channels[i].base + IDE_REGISTER_LBA1);
uint8_t ch = _inb(ide_channels[i].base + IDE_REGISTER_LBA2);
if(cl == 0x14 && ch == 0xEB) /* PATAPI */
type = 1;
else if(cl == 0x69 && ch == 0x96) /* SATAPI */
type = 1;
else
{
/* Unknown Type */
count++;
continue;
}
/* Identify */
ide_write(i, IDE_REGISTER_COMMAND, IDE_COMMAND_PACKET);
ide_delay(i);
}
/* Step 5. Read identification space */
_insw(ide_channels[i].base + IDE_REGISTER_DATA, 256, (uint8_t*)buf);
/* Step 6. Read device parameters */
ide_devices[count].present = 1;
ide_devices[count].type = type;
ide_devices[count].channel = i;
ide_devices[count].drive = j;
ide_devices[count].signature = (*(uint16_t*)(buf));
ide_devices[count].capabilities = (*(uint16_t*)(buf + 49));
ide_devices[count].commandset = (*(uint32_t*)(buf + 82));
/* Step 7. Get geometry */
lba28 = (*(uint32_t*)(buf + 60));
lba48 = (*(uint64_t*)(buf + 100));
if(lba48)
{
ide_devices[count].totalsectors = lba48;
ide_devices[count].cylinders = (*(uint16_t*)(buf + 1));
ide_devices[count].headspercylinder = (*(uint16_t*)(buf + 3));
ide_devices[count].secsperhead = (*(uint64_t*)(buf + 6));
ide_devices[count].flags |= 0x1;
}
else if(lba28 && !lba48)
{
ide_devices[count].totalsectors = lba28;
ide_devices[count].cylinders = (*(uint16_t*)(buf + 1));
ide_devices[count].headspercylinder = (*(uint16_t*)(buf + 3));
ide_devices[count].secsperhead = (*(uint64_t*)(buf + 6));
}
else
{
ide_devices[count].totalsectors = 0;
ide_devices[count].cylinders = 0;
ide_devices[count].headspercylinder = 0;
ide_devices[count].secsperhead = 0;
}
/* Register filesystem */
ide_dev[count].real_device = &(ide_channels[0]);
ide_dev[count].type = TYPECODE_DISK;
ide_dev[count].generic_device = &ide_gbd[count];
ide_dev[count].io_address = count;
/* Setup ide device */
ide_gbd[count].device = &ide_dev[count];
ide_gbd[count].write_block = ide_write_block;
ide_gbd[count].read_block = ide_read_block;
ide_gbd[count].block_size = ide_get_sectorsize;
ide_gbd[count].total_blocks = ide_get_sectorcount;
device_register(&ide_dev[count]);
/* Increase count */
count++;
}
}
return 0;
}
