void
m68hc11sio_tx_poll (struct hw *me, void *data)
{
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
controller = hw_data (me);
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
cpu->ios[M6811_SCSR] |= M6811_TDRE;
cpu->ios[M6811_SCSR] |= M6811_TC;
/* Transmitter is enabled and we have something to send. */
if ((cpu->ios[M6811_SCCR2] & M6811_TE) && controller->tx_has_char)
{
cpu->ios[M6811_SCSR] &= ~M6811_TDRE;
cpu->ios[M6811_SCSR] &= ~M6811_TC;
controller->tx_has_char = 0;
switch (controller->backend)
{
case sio_tcp:
dv_sockser_write (sd, controller->tx_char);
break;
case sio_stdio:
sim_io_write_stdout (sd, &controller->tx_char, 1);
sim_io_flush_stdout (sd);
break;
default:
break;
}
}
if (controller->tx_poll_event)
{
hw_event_queue_deschedule (me, controller->tx_poll_event);
controller->tx_poll_event = 0;
}
if ((cpu->ios[M6811_SCCR2] & M6811_TE)
&& ((cpu->ios[M6811_SCSR] & M6811_TC) == 0))
{
unsigned long clock_cycle;
/* Compute CPU clock cycles to wait for the next character. */
clock_cycle = controller->data_length * controller->baud_cycle;
controller->tx_poll_event = hw_event_queue_schedule (me, clock_cycle,
m68hc11sio_tx_poll,
NULL);
}
interrupts_update_pending (&cpu->cpu_interrupts);
}
static unsigned
m68hc11spi_io_read_buffer (struct hw *me,
void *dest,
int space,
unsigned_word base,
unsigned nr_bytes)
{
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu *cpu;
unsigned8 val;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
controller = hw_data (me);
switch (base)
{
case M6811_SPSR:
controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
& (M6811_SPIF | M6811_WCOL | M6811_MODF);
case M6811_SPCR:
val = cpu->ios[base];
break;
case M6811_SPDR:
if (controller->rx_clear_scsr)
{
cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
controller->rx_clear_scsr = 0;
interrupts_update_pending (&cpu->cpu_interrupts);
}
val = controller->rx_char;
break;
default:
return 0;
}
*((unsigned8*) dest) = val;
return 1;
}
static unsigned
m68hc11spi_io_write_buffer (struct hw *me,
const void *source,
int space,
unsigned_word base,
unsigned nr_bytes)
{
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu *cpu;
unsigned8 val;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
controller = hw_data (me);
val = *((const unsigned8*) source);
switch (base)
{
case M6811_SPCR:
cpu->ios[M6811_SPCR] = val;
/* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock.
We have to drive the clock pin and need a 2x faster clock. */
switch (val & (M6811_SPR1 | M6811_SPR0))
{
case 0:
controller->clock = 1;
break;
case 1:
controller->clock = 2;
break;
case 2:
controller->clock = 8;
break;
default:
controller->clock = 16;
break;
}
/* Set the clock pin. */
if ((val & M6811_CPOL)
&& (controller->spi_event == 0
|| ((val & M6811_CPHA) && controller->mode == 1)))
controller->clk_pin = 1;
else
controller->clk_pin = 0;
set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
break;
/* Can't write to SPSR. */
case M6811_SPSR:
break;
case M6811_SPDR:
if (!(cpu->ios[M6811_SPCR] & M6811_SPE))
{
return 0;
}
if (controller->rx_clear_scsr)
{
cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
controller->rx_clear_scsr = 0;
interrupts_update_pending (&cpu->cpu_interrupts);
}
/* If transfer is taking place, a write to SPDR
generates a collision. */
if (controller->spi_event)
{
cpu->ios[M6811_SPSR] |= M6811_WCOL;
break;
}
/* Refuse the write if there was no read of SPSR. */
/* ???? TBD. */
/* Prepare to send a byte. */
controller->tx_char = val;
controller->mode = SPI_START_BYTE;
/* Toggle clock pin internal value when CPHA is 0 so that
it will really change in the middle of a bit. */
if (!(cpu->ios[M6811_SPCR] & M6811_CPHA))
controller->clk_pin = ~controller->clk_pin;
cpu->ios[M6811_SPDR] = val;
/* Activate transmission. */
m68hc11spi_clock (me, NULL);
break;
default:
return 0;
}
return nr_bytes;
}
void
m68hc11spi_clock (struct hw *me, void *data)
{
SIM_DESC sd;
struct m68hc11spi* controller;
sim_cpu *cpu;
int check_interrupt = 0;
controller = hw_data (me);
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
/* Cleanup current event. */
if (controller->spi_event)
{
hw_event_queue_deschedule (me, controller->spi_event);
controller->spi_event = 0;
}
/* Change a bit of data at each two SPI event. */
if (controller->mode == SPI_START_BIT)
{
/* Reflect the bit value on bit 2 of port D. */
set_bit_port (me, cpu, M6811_PORTD, (1 << 2),
(controller->tx_char & (1 << controller->tx_bit)));
controller->tx_bit--;
controller->mode = SPI_MIDDLE_BIT;
}
else if (controller->mode == SPI_MIDDLE_BIT)
{
controller->mode = SPI_START_BIT;
}
if (controller->mode == SPI_START_BYTE)
{
/* Start a new SPI transfer. */
/* TBD: clear SS output. */
controller->mode = SPI_START_BIT;
controller->tx_bit = 7;
set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
}
else
{
/* Change the SPI clock at each event on bit 4 of port D. */
controller->clk_pin = ~controller->clk_pin;
set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
}
/* Transmit is now complete for this byte. */
if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
{
controller->rx_clear_scsr = 0;
cpu->ios[M6811_SPSR] |= M6811_SPIF;
if (cpu->ios[M6811_SPCR] & M6811_SPIE)
check_interrupt = 1;
}
else
{
controller->spi_event = hw_event_queue_schedule (me, controller->clock,
m68hc11spi_clock,
NULL);
}
if (check_interrupt)
interrupts_update_pending (&cpu->cpu_interrupts);
}
static unsigned
m68hc11sio_io_write_buffer (struct hw *me,
const void *source,
int space,
unsigned_word base,
unsigned nr_bytes)
{
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
unsigned8 val;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
controller = hw_data (me);
val = *((const unsigned8*) source);
switch (base)
{
case M6811_BAUD:
{
long divisor;
long baud;
cpu->ios[M6811_BAUD] = val;
switch (val & (M6811_SCP1|M6811_SCP0))
{
case M6811_BAUD_DIV_1:
divisor = 1 * 16;
break;
case M6811_BAUD_DIV_3:
divisor = 3 * 16;
break;
case M6811_BAUD_DIV_4:
divisor = 4 * 16;
break;
default:
case M6811_BAUD_DIV_13:
divisor = 13 * 16;
break;
}
val &= (M6811_SCR2|M6811_SCR1|M6811_SCR0);
divisor *= (1 << val);
baud = (cpu->cpu_frequency / 4) / divisor;
HW_TRACE ((me, "divide rate %ld, baud rate %ld",
divisor, baud));
controller->baud_cycle = divisor;
}
break;
case M6811_SCCR1:
{
if (val & M6811_M)
controller->data_length = 11;
else
controller->data_length = 10;
cpu->ios[M6811_SCCR1] = val;
}
break;
case M6811_SCCR2:
if ((val & M6811_RE) == 0)
{
val &= ~(M6811_RDRF|M6811_IDLE|M6811_OR|M6811_NF|M6811_NF);
val |= (cpu->ios[M6811_SCCR2]
& (M6811_RDRF|M6811_IDLE|M6811_OR|M6811_NF|M6811_NF));
cpu->ios[M6811_SCCR2] = val;
break;
}
/* Activate reception. */
if (controller->rx_poll_event == 0)
{
long clock_cycle;
/* Compute CPU clock cycles to wait for the next character. */
clock_cycle = controller->data_length * controller->baud_cycle;
controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
m68hc11sio_rx_poll,
NULL);
}
cpu->ios[M6811_SCCR2] = val;
interrupts_update_pending (&cpu->cpu_interrupts);
break;
/* No effect. */
case M6811_SCSR:
return 1;
case M6811_SCDR:
if (!(cpu->ios[M6811_SCSR] & M6811_TDRE))
{
return 0;
}
controller->tx_char = val;
controller->tx_has_char = 1;
if ((cpu->ios[M6811_SCCR2] & M6811_TE)
&& controller->tx_poll_event == 0)
{
m68hc11sio_tx_poll (me, NULL);
}
return 1;
default:
return 0;
}
return nr_bytes;
}
void
m68hc11sio_rx_poll (struct hw *me, void *data)
{
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
char cc;
int cnt;
int check_interrupt = 0;
controller = hw_data (me);
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
switch (controller->backend)
{
case sio_tcp:
cnt = dv_sockser_read (sd);
if (cnt != -1)
{
cc = (char) cnt;
cnt = 1;
}
break;
case sio_stdio:
cnt = sim_io_poll_read (sd, 0 /* stdin */, &cc, 1);
break;
default:
cnt = 0;
break;
}
if (cnt == 1)
{
/* Raise the overrun flag if the previous character was not read. */
if (cpu->ios[M6811_SCSR] & M6811_RDRF)
cpu->ios[M6811_SCSR] |= M6811_OR;
cpu->ios[M6811_SCSR] |= M6811_RDRF;
controller->rx_char = cc;
controller->rx_clear_scsr = 0;
check_interrupt = 1;
}
else
{
/* handle idle line detect here. */
;
}
if (controller->rx_poll_event)
{
hw_event_queue_deschedule (me, controller->rx_poll_event);
controller->rx_poll_event = 0;
}
if (cpu->ios[M6811_SCCR2] & M6811_RE)
{
unsigned long clock_cycle;
/* Compute CPU clock cycles to wait for the next character. */
clock_cycle = controller->data_length * controller->baud_cycle;
controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
m68hc11sio_rx_poll,
NULL);
}
if (check_interrupt)
interrupts_update_pending (&cpu->cpu_interrupts);
}
static unsigned
m68hc11tim_io_write_buffer (struct hw *me,
const void *source,
int space,
unsigned_word base,
unsigned nr_bytes)
{
SIM_DESC sd;
struct m68hc11tim *controller;
sim_cpu *cpu;
unsigned8 val, n;
signed64 adj;
int reset_compare = 0;
int reset_overflow = 0;
int cnt = 0;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
controller = hw_data (me);
while (nr_bytes)
{
val = *((const unsigned8*) source);
switch (base)
{
/* Set the timer counter low part, trying to preserve the low part.
We compute the absolute cycle adjustment that we have to apply
to obtain the timer current value. Computation must be made
in 64-bit to avoid overflow problems. */
case M6811_TCTN_L:
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ (controller->clock_prescaler * (signed64) 256)) & 0x0FF;
adj = cpu->cpu_absolute_cycle
- (adj * controller->clock_prescaler * (signed64) 256)
- ((signed64) adj * controller->clock_prescaler);
controller->tcnt_adjust = adj;
reset_compare = 1;
reset_overflow = 1;
break;
case M6811_TCTN_H:
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ controller->clock_prescaler) & 0x0ff;
adj = cpu->cpu_absolute_cycle
- ((signed64) val * controller->clock_prescaler * (signed64) 256)
- (adj * controller->clock_prescaler);
controller->tcnt_adjust = adj;
reset_compare = 1;
reset_overflow = 1;
break;
case M6811_TMSK2:
/* Timer prescaler cannot be changed after 64 bus cycles. */
if (cpu->cpu_absolute_cycle >= 64)
{
val &= ~(M6811_PR1 | M6811_PR0);
val |= cpu->ios[M6811_TMSK2] & (M6811_PR1 | M6811_PR0);
}
switch (val & (M6811_PR1 | M6811_PR0))
{
case 0:
n = 1;
break;
case M6811_PR0:
n = 4;
break;
case M6811_PR1:
n = 8;
break;
default:
case M6811_PR1 | M6811_PR0:
n = 16;
break;
}
if (cpu->cpu_absolute_cycle < 64)
{
reset_overflow = 1;
controller->clock_prescaler = n;
}
cpu->ios[base] = val;
interrupts_update_pending (&cpu->cpu_interrupts);
break;
case M6811_PACTL:
n = (1 << ((val & (M6811_RTR1 | M6811_RTR0))));
cpu->ios[base] = val;
controller->rti_delay = (long) (n) * 8192;
m68hc11tim_timer_event (me, (void*) (RTI_EVENT| 0x100));
break;
case M6811_TFLG2:
val &= cpu->ios[M6811_TFLG2];
cpu->ios[M6811_TFLG2] &= ~val;
interrupts_update_pending (&cpu->cpu_interrupts);
break;
case M6811_TMSK1:
cpu->ios[M6811_TMSK1] = val;
interrupts_update_pending (&cpu->cpu_interrupts);
reset_compare = 1;
break;
case M6811_TFLG1:
val &= cpu->ios[M6811_TFLG1];
cpu->ios[M6811_TFLG1] &= ~val;
interrupts_update_pending (&cpu->cpu_interrupts);
break;
case M6811_TOC1:
case M6811_TOC2:
case M6811_TOC3:
case M6811_TOC4:
case M6811_TOC5:
cpu->ios[base] = val;
reset_compare = 1;
break;
case M6811_TCTL1:
case M6811_TCTL2:
cpu->ios[base] = val;
break;
default:
cpu->ios[base] = val;
break;
}
base++;
nr_bytes--;
cnt++;
source = (char*) source + 1;
}
/* Re-compute the next timer compare event. */
if (reset_compare)
{
m68hc11tim_timer_event (me, (void*) (COMPARE_EVENT));
}
if (reset_overflow)
{
m68hc11tim_timer_event (me, (void*) (OVERFLOW_EVENT| 0x100));
}
return cnt;
}
static void
m68hc11tim_timer_event (struct hw *me, void *data)
{
SIM_DESC sd;
struct m68hc11tim *controller;
sim_cpu *cpu;
enum event_type type;
unsigned long delay;
struct hw_event **eventp;
int check_interrupt = 0;
unsigned mask;
unsigned flags;
unsigned long tcnt_internal;
unsigned long tcnt, tcnt_prev;
signed64 tcnt_insn_end;
signed64 tcnt_insn_start;
int i;
sim_events *events;
controller = hw_data (me);
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
type = (enum event_type) ((long) data) & 0x0FF;
events = STATE_EVENTS (sd);
delay = 0;
switch (type)
{
case COP_EVENT:
eventp = &controller->cop_timer_event;
delay = controller->cop_delay;
delay = controller->cop_prev_interrupt + controller->cop_delay;
controller->cop_prev_interrupt = delay;
delay = delay - cpu->cpu_absolute_cycle;
check_interrupt = 1;
delay += events->nr_ticks_to_process;
break;
case RTI_EVENT:
eventp = &controller->rti_timer_event;
delay = controller->rti_prev_interrupt + controller->rti_delay;
if (((long) (data) & 0x0100) == 0)
{
cpu->ios[M6811_TFLG2] |= M6811_RTIF;
check_interrupt = 1;
controller->rti_prev_interrupt = delay;
delay += controller->rti_delay;
}
delay = delay - cpu->cpu_absolute_cycle;
delay += events->nr_ticks_to_process;
break;
case OVERFLOW_EVENT:
/* Compute the 68HC11 internal free running counter. */
tcnt_internal = (cpu->cpu_absolute_cycle - controller->tcnt_adjust);
/* We must take into account the prescaler that comes
before the counter (it's a power of 2). */
tcnt_internal &= 0x0ffff * controller->clock_prescaler;
/* Compute the time when the overflow will occur. It occurs when
the counter increments from 0x0ffff to 0x10000 (and thus resets). */
delay = (0x10000 * controller->clock_prescaler) - tcnt_internal;
/* The 'nr_ticks_to_process' will be subtracted when the event
is scheduled. */
delay += events->nr_ticks_to_process;
eventp = &controller->tof_timer_event;
if (((long) (data) & 0x100) == 0)
{
cpu->ios[M6811_TFLG2] |= M6811_TOF;
check_interrupt = 1;
}
break;
case COMPARE_EVENT:
/* Compute value of TCNT register (64-bit precision) at beginning
and end of instruction. */
tcnt_insn_end = (cpu->cpu_absolute_cycle - controller->tcnt_adjust);
tcnt_insn_start = (tcnt_insn_end - cpu->cpu_current_cycle);
/* TCNT value at beginning of current instruction. */
tcnt_prev = (tcnt_insn_start / controller->clock_prescaler) & 0x0ffff;
/* TCNT value at end of current instruction. */
tcnt = (tcnt_insn_end / controller->clock_prescaler) & 0x0ffff;
/* We must take into account the prescaler that comes
before the counter (it's a power of 2). */
tcnt_internal = tcnt_insn_end;
tcnt_internal &= 0x0ffff * controller->clock_prescaler;
flags = cpu->ios[M6811_TMSK1];
mask = 0x80;
delay = 65536 * controller->clock_prescaler;
/* Scan each output compare register to see if one matches
the free running counter. Set the corresponding OCi flag
if the output compare is enabled. */
for (i = M6811_TOC1; i <= M6811_TOC5; i += 2, mask >>= 1)
{
unsigned long compare;
compare = (cpu->ios[i] << 8) + cpu->ios[i + 1];
/* See if compare is reached; handle wrap arround. */
if ((compare >= tcnt_prev && compare <= tcnt && tcnt_prev < tcnt)
|| (compare >= tcnt_prev && tcnt_prev > tcnt)
|| (compare < tcnt && tcnt_prev > tcnt))
{
unsigned dt;
if (compare > tcnt)
dt = 0x10000 - compare - tcnt;
else
dt = tcnt - compare;
cpu->ios[M6811_TFLG1] |= mask;
/* Raise interrupt now at the correct CPU cycle so that
we can find the interrupt latency. */
cpu->cpu_absolute_cycle -= dt;
interrupts_update_pending (&cpu->cpu_interrupts);
cpu->cpu_absolute_cycle += dt;
}
/* Compute how many times for the next match.
Use the internal counter value to take into account the
prescaler accurately. */
compare = compare * controller->clock_prescaler;
if (compare > tcnt_internal)
compare = compare - tcnt_internal;
else
compare = compare - tcnt_internal
+ 65536 * controller->clock_prescaler;
if (compare < delay)
delay = compare;
}
/* Deactivate the compare timer if no output compare is enabled. */
if ((flags & 0xF8) == 0)
delay = 0;
else
delay += events->nr_ticks_to_process;
eventp = &controller->cmp_timer_event;
break;
default:
eventp = 0;
break;
}
if (*eventp)
{
hw_event_queue_deschedule (me, *eventp);
*eventp = 0;
}
if (delay != 0)
{
*eventp = hw_event_queue_schedule (me, delay,
m68hc11tim_timer_event,
(void*) type);
}
if (check_interrupt)
interrupts_update_pending (&cpu->cpu_interrupts);
}