static void __init prpmc750_map_io(void)
{
io_block_mapping(PRPMC750_ISA_IO_BASE, PRPMC750_ISA_IO_BASE,
0x10000000, _PAGE_IO);
#if 0
io_block_mapping(0xf0000000, 0xc0000000, 0x08000000, _PAGE_IO);
#endif
io_block_mapping(0xf8000000, 0xf8000000, 0x08000000, _PAGE_IO);
}
static void __init ppc7d_map_io(void)
{
/* remove temporary mapping */
mtspr(SPRN_DBAT3U, 0x00000000);
mtspr(SPRN_DBAT3L, 0x00000000);
io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO);
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
}
/* Map the IMMR, plus anything else we can cover
* in that upper space according to the memory controller
* chip select mapping. Grab another bunch of space
* below that for stuff we can't cover in the upper.
*/
static void __init
m8260_map_io(void)
{
uint addr;
/* Map IMMR region to a 256MB BAT */
addr = (cpm2_immr != NULL) ? (uint)cpm2_immr : CPM_MAP_ADDR;
io_block_mapping(addr, addr, 0x10000000, _PAGE_IO);
/* Map I/O region to a 256MB BAT */
io_block_mapping(IO_VIRT_ADDR, IO_PHYS_ADDR, 0x10000000, _PAGE_IO);
}
void __init
ppc4xx_map_io(void)
{
io_block_mapping(PPC4xx_ONB_IO_VADDR,
PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO);
#ifdef CONFIG_PCI
io_block_mapping(PPC4xx_PCI_IO_VADDR,
PPC4xx_PCI_IO_PADDR, PPC4xx_PCI_IO_SIZE, _PAGE_IO);
io_block_mapping(PPC4xx_PCI_CFG_VADDR,
PPC4xx_PCI_CFG_PADDR, PPC4xx_PCI_CFG_SIZE, _PAGE_IO);
io_block_mapping(PPC4xx_PCI_LCFG_VADDR,
PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO);
#endif
}
void __init
bubinga_map_io(void)
{
ppc4xx_map_io();
io_block_mapping(BUBINGA_RTC_VADDR,
BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
}
void __init
sycamore_map_io(void)
{
ppc4xx_map_io();
io_block_mapping(SYCAMORE_RTC_VADDR,
SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
}
void __init
walnut_map_io(void)
{
ppc4xx_map_io();
io_block_mapping(WALNUT_RTC_VADDR,
WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
}
static void __init taiga_map_io(void)
{
/* PCI IO mapping */
io_block_mapping(TAIGA_PCI_IO_BASE_VIRT, TAIGA_PCI_IO_BASE_PHYS,
0x00800000, _PAGE_IO);
/* Tsi108 CSR mapping */
io_block_mapping(TSI108_CSR_ADDR_VIRT, TSI108_CSR_ADDR_PHYS,
0x100000, _PAGE_IO);
tsi108_csr_base = TSI108_CSR_ADDR_VIRT;
/* PCI Config mapping */
io_block_mapping(TAIGA_PCI_CFG_BASE_VIRT, TAIGA_PCI_CFG_BASE_PHYS,
TAIGA_PCI_CFG_SIZE, _PAGE_IO);
tsi108_pci_cfg_base = TAIGA_PCI_CFG_BASE_VIRT;
/* NVRAM mapping */
io_block_mapping(TAIGA_NVRAM_BASE_ADDR, TAIGA_NVRAM_BASE_ADDR,
TAIGA_NVRAM_SIZE, _PAGE_IO);
}
/**************************************************************************
* FUNCTION: chestnut_map_io
*
* DESCRIPTION: configure fixed memory-mapped IO
*
****/
static void __init
chestnut_map_io(void)
{
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
_PAGE_IO);
#endif
}
void __init
mpc52xx_map_io(void)
{
/* Here we map the MBAR and the whole upper zone. MBAR is only
64k but we can't map only 64k with BATs. Map the whole
0xf0000000 range is ok and helps eventual lpb devices placed there */
io_block_mapping(
MPC52xx_MBAR_VIRT, MPC52xx_MBAR, 0x10000000, _PAGE_IO);
}
void __init
board_io_mapping(void)
{
int i;
io_block_mapping(OAKNET_IO_VADDR,
OAKNET_IO_PADDR, OAKNET_IO_SIZE, _PAGE_IO);
}
void __init
board_io_mapping(void)
{
int i;
for (i = 0; i < 16; i++) {
unsigned long v, p;
/* 0x400x0000 -> 0xe00x0000 */
p = 0x40000000 | (i << 16);
v = STBx25xx_IO_BASE | (i << 16);
io_block_mapping(v, p, PAGE_SIZE,
_PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) |
_PAGE_GUARDED);
}
}
static void __init
mcpn765_map_io(void)
{
io_block_mapping(0xfe800000, 0xfe800000, 0x00800000, _PAGE_IO);
}
static void __init
pplus_map_io(void)
{
io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xf0000000, 0xc0000000, 0x08000000, _PAGE_IO);
}
static void __init pplus_map_io(void)
{
io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
_PAGE_IO);
io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
}
static void __init
lopec_map_io(void)
{
io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
}
static void __init
mvme5100_map_io(void)
{
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
ioremap_base = 0xfe000000;
}
static void __init
pcore_map_io(void)
{
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
}
/* Map the IMMR, plus anything else we can cover
* in that upper space according to the memory controller
* chip select mapping. Grab another bunch of space
* below that for stuff we can't cover in the upper.
*/
static void __init
m8260_map_io(void)
{
io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xe0000000, 0xe0000000, 0x10000000, _PAGE_IO);
}
static void __init
sandpoint_map_io(void)
{
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
}
void __init
ash_map_io(void)
{
ppc4xx_map_io();
io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
}
static void __init
tqm834x_map_io(void)
{
/* we steal the lowest ioremap addr for virt space */
io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
}
