/* Creates shader:
* (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x
* end
*/
static struct fd3_shader_stateobj *
create_solid_fp(struct pipe_context *pctx)
{
struct fd3_shader_stateobj *so;
struct ir3_shader *ir = ir3_shader_create();
struct ir3_instruction *instr;
/* (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x */
instr = ir3_instr_create(ir, 1, 0); /* mov/cov instructions have no opc */
instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
instr->repeat = 3;
instr->cat1.src_type = TYPE_F16;
instr->cat1.dst_type = TYPE_F16;
ir3_reg_create(instr, regid(0,0), IR3_REG_HALF); /* hr0.x */
ir3_reg_create(instr, regid(0,0), IR3_REG_HALF | /* (r)hc0.x */
IR3_REG_CONST | IR3_REG_R);
/* end */
instr = ir3_instr_create(ir, 0, OPC_END);
so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
if (!so)
return NULL;
so->color_regid = regid(0,0);
so->half_precision = true;
so->inputs_count = 0;
so->total_in = 0;
return so;
}
/* a bit of sadness.. we can't have "holes" in inputs from PoV of
* register assignment, they still need to be grouped together. So
* we need to insert dummy/padding instruction for grouping, and
* then take it back out again before anyone notices.
*/
static void
pad_and_group_input(struct ir3_instruction **input, unsigned n)
{
int i, mask = 0;
struct ir3_block *block = NULL;
for (i = n - 1; i >= 0; i--) {
struct ir3_instruction *instr = input[i];
if (instr) {
block = instr->block;
} else if (block) {
instr = ir3_NOP(block);
ir3_reg_create(instr, 0, IR3_REG_SSA); /* dummy dst */
input[i] = instr;
mask |= (1 << i);
}
}
group_n(&arr_ops_in, input, n);
for (i = 0; i < n; i++) {
if (mask & (1 << i))
input[i] = NULL;
}
}
static void arr_insert_mov_in(void *arr, int idx, struct ir3_instruction *instr)
{
/* so, we can't insert a mov in front of a meta:in.. and the downstream
* instruction already has a pointer to 'instr'. So we cheat a bit and
* morph the meta:in instruction into a mov and insert a new meta:in
* in front.
*/
struct ir3_instruction *in;
debug_assert(instr->regs_count == 1);
in = ir3_instr_create(instr->block, OPC_META_INPUT);
in->inout.block = instr->block;
ir3_reg_create(in, instr->regs[0]->num, 0);
/* create src reg for meta:in and fixup to now be a mov: */
ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = in;
instr->opc = OPC_MOV;
instr->cat1.src_type = TYPE_F32;
instr->cat1.dst_type = TYPE_F32;
((struct ir3_instruction **)arr)[idx] = in;
}
/* Creates shader:
* (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x
* (rpt5)nop
* sam (f32)(xyzw)r0.x, r0.z, s#0, t#0
* (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x
* end
*/
static struct fd3_shader_stateobj *
create_blit_fp(struct pipe_context *pctx)
{
struct fd3_shader_stateobj *so;
struct ir3_shader *ir = ir3_shader_create();
struct ir3_instruction *instr;
/* (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x */
instr = ir3_instr_create(ir, 2, OPC_BARY_F);
instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
instr->repeat = 1;
ir3_reg_create(instr, regid(0,2), IR3_REG_EI); /* (ei)r0.z */
ir3_reg_create(instr, 0, IR3_REG_R | /* (r)0 */
IR3_REG_IMMED)->iim_val = 0;
ir3_reg_create(instr, regid(0,0), 0); /* r0.x */
/* (rpt5)nop */
instr = ir3_instr_create(ir, 0, OPC_NOP);
instr->repeat = 5;
/* sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 */
instr = ir3_instr_create(ir, 5, OPC_SAM);
instr->cat5.samp = 0;
instr->cat5.tex = 0;
instr->cat5.type = TYPE_F32;
ir3_reg_create(instr, regid(0,0), /* (xyzw)r0.x */
0)->wrmask = 0xf;
ir3_reg_create(instr, regid(0,2), 0); /* r0.z */
/* (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x */
instr = ir3_instr_create(ir, 1, 0); /* mov/cov instructions have no opc */
instr->flags = IR3_INSTR_SY;
instr->repeat = 3;
instr->cat1.src_type = TYPE_F32;
instr->cat1.dst_type = TYPE_F16;
ir3_reg_create(instr, regid(0,0), IR3_REG_HALF); /* hr0.x */
ir3_reg_create(instr, regid(0,0), IR3_REG_R); /* (r)r0.x */
/* end */
instr = ir3_instr_create(ir, 0, OPC_END);
so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
if (!so)
return NULL;
so->color_regid = regid(0,0);
so->half_precision = true;
so->inputs_count = 1;
so->inputs[0].inloc = 8;
so->inputs[0].compmask = 0x3;
so->total_in = 2;
so->samplers_count = 1;
so->vpsrepl[0] = 0x99999999;
so->vpsrepl[1] = 0x99999999;
so->vpsrepl[2] = 0x99999999;
so->vpsrepl[3] = 0x99999999;
return so;
}