void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
if (is_A_Module(moduleInstance))
{
EUSCI_A_SPI_disableInterrupt(moduleInstance, mask);
} else
{
EUSCI_B_SPI_disableInterrupt(moduleInstance, mask);
}
}
void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
{
if (is_A_Module(moduleInstance))
{
EUSCI_A_SPI_clearInterruptFlag(moduleInstance, mask);
} else
{
EUSCI_B_SPI_clearInterruptFlag(moduleInstance, mask);
}
}
uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
{
if (is_A_Module(moduleInstance))
{
return EUSCI_A_SPI_getInterruptStatus(moduleInstance, mask);
} else
{
return EUSCI_B_SPI_getInterruptStatus(moduleInstance, mask);
}
}
uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
if (is_A_Module(moduleInstance))
{
return EUSCI_A_SPI_getTransmitBufferAddressForDMA(moduleInstance);
} else
{
return EUSCI_B_SPI_getTransmitBufferAddressForDMA(moduleInstance);
}
}
uint_fast8_t SPI_isBusy(uint32_t moduleInstance)
{
if (is_A_Module(moduleInstance))
{
return EUSCI_A_SPI_isBusy(moduleInstance);
} else
{
return EUSCI_B_SPI_isBusy(moduleInstance);
}
}
uint8_t SPI_receiveData(uint32_t moduleInstance)
{
if (is_A_Module(moduleInstance))
{
return EUSCI_A_SPI_receiveData(moduleInstance);
} else
{
return EUSCI_B_SPI_receiveData(moduleInstance);
}
}
void SPI_disableModule(uint32_t moduleInstance)
{
if (is_A_Module(moduleInstance))
{
EUSCI_A_SPI_disable(moduleInstance);
} else
{
EUSCI_B_SPI_disable(moduleInstance);
}
}
void SPI_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
{
if (is_A_Module(moduleInstance))
{
EUSCI_A_SPI_transmitData(moduleInstance, transmitData);
} else
{
EUSCI_B_SPI_transmitData(moduleInstance, transmitData);
}
}
void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
uint_fast16_t clockPhase, uint_fast16_t clockPolarity)
{
if (is_A_Module(moduleInstance))
{
EUSCI_A_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
clockPolarity);
} else
{
EUSCI_B_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
clockPolarity);
}
}
void SPI_changeMasterClock(uint32_t moduleInstance,
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
if (is_A_Module(moduleInstance))
{
EUSCI_A_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
desiredSpiClock);
} else
{
EUSCI_B_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
desiredSpiClock);
}
}
void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
uint_fast8_t select4PinFunctionality)
{
if (is_A_Module(moduleInstance))
{
EUSCI_A_SPI_select4PinFunctionality(moduleInstance,
select4PinFunctionality);
} else
{
EUSCI_B_SPI_select4PinFunctionality(moduleInstance,
select4PinFunctionality);
}
}
uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
{
if (is_A_Module(moduleInstance))
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
& HWREG16(moduleInstance + OFS_UCA0IE);
} else
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
& HWREG16(moduleInstance + OFS_UCB0IE);
}
}
uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
{
if (is_A_Module(moduleInstance))
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
& EUSCI_A_CMSIS(moduleInstance)->IE;
} else
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
& EUSCI_B_CMSIS(moduleInstance)->IE;
}
}
bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
{
if (is_A_Module(moduleInstance))
{
ASSERT(
(EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_A_SPI_3PIN == config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* UCMST = Master mode
* UCSYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
+ UCMODE_3 + UCSYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ UCMST + UCSYNC + config->spiMode);
EUSCI_A_CMSIS(moduleInstance)->rBRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
//No modulation
EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = 0;
return true;
} else
{
ASSERT(
(EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_B_SPI_3PIN == config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* UCMST = Master mode
* UCSYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
+ UCMODE_3 + UCSYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ UCMST + UCSYNC + config->spiMode);
EUSCI_B_CMSIS(moduleInstance)->rBRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
return true;
}
}
bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
{
if (is_A_Module(moduleInstance))
{
ASSERT(
(EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_A_SPI_3PIN == config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
| (config->clockPhase + config->clockPolarity
+ config->msbFirst + UCSYNC + config->spiMode);
return true;
} else
{
ASSERT(
(EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_B_SPI_3PIN == config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
| (config->clockPhase + config->clockPolarity
+ config->msbFirst + UCSYNC + config->spiMode);
return true;
}
}
bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
{
/* Returning false if we are not divisible */
if((config->clockSourceFrequency
% config->desiredSpiClock) != 0)
{
return false;
}
if (is_A_Module(moduleInstance))
{
ASSERT(
(EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_A_SPI_3PIN == config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* EUSCI_A_CTLW0_MST = Master mode
* EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
EUSCI_A_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
//No modulation
EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0;
return true;
} else
{
ASSERT(
(EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_B_SPI_3PIN == config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* EUSCI_A_CTLW0_MST = Master mode
* EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
EUSCI_B_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
return true;
}
}
