static int dpe_on(struct platform_device *pdev)
{
int ret = 0;
struct k3_fb_data_type *k3fd = NULL;
BUG_ON(pdev == NULL);
k3fd = platform_get_drvdata(pdev);
BUG_ON(k3fd == NULL);
K3_FB_DEBUG("fb%d, +.\n", k3fd->index);
/* dis reset DSI */
if (is_mipi_panel(k3fd)) {
if (is_dual_mipi_panel(k3fd)) {
outp32(k3fd->crgperi_base + PERRSTDIS3_OFFSET, 0x00030000);
} else {
outp32(k3fd->crgperi_base + PERRSTDIS3_OFFSET, 0x00020000);
}
}
if (k3fd->index != PRIMARY_PANEL_IDX) {
if (k3fd_list[PRIMARY_PANEL_IDX] &&
(k3fd_list[PRIMARY_PANEL_IDX]->panel_info.vsync_ctrl_type & VSYNC_CTRL_CLK_OFF)) {
K3_FB_DEBUG("fb%d, pdp clk enable!\n", k3fd->index);
dpe_clk_enable(k3fd_list[PRIMARY_PANEL_IDX]);
}
}
dpe_regulator_enable(k3fd);
dpe_init(k3fd);
if (is_ldi_panel(k3fd)) {
k3fd->panel_info.lcd_init_step = LCD_INIT_POWER_ON;
ret = panel_next_on(pdev);
}
ret = panel_next_on(pdev);
if (k3fd->panel_info.vsync_ctrl_type == VSYNC_CTRL_NONE) {
dpe_irq_enable(k3fd);
dpe_interrupt_unmask(k3fd);
}
#if 0
if (k3fd->index == PRIMARY_PANEL_IDX) {
enable_ldi_pdp(k3fd);
} else if (k3fd->index == EXTERNAL_PANEL_IDX) {
enable_ldi_sdp(k3fd);
} else if (k3fd->index == AUXILIARY_PANEL_IDX) {
; /* do nothing */
} else {
K3_FB_ERR("fb%d, not support this device!\n", k3fd->index);
}
#endif
K3_FB_DEBUG("fb%d, -.\n", k3fd->index);
return ret;
}
void enable_clk_panel(struct hisi_fb_data_type *hisifd)
{
char __iomem *dss_base = NULL;
uint32_t val = 0;
int prev_refcount = 0;
BUG_ON(hisifd == NULL);
dss_base = hisifd->dss_base;
down(&hisi_fb_dss_panel_clk_sem);
prev_refcount = panel_refcount++;
if (!prev_refcount) {
/* de-reset status */
val =0x0;
if (is_mipi_panel(hisifd)) {
val |= PDP_DSI0_DIS_RST_CFG;
}
if (is_dual_mipi_panel(hisifd)) {
val |= PDP_DSI1_DIS_RST_CFG;
}
outp32(dss_base + DSS_GLB_DIS_RST_CFG, val);
/* enable clk */
val = 0x0;
if (is_mipi_panel(hisifd)) {
val |= PDP_DSI0_EN_CLK_CFG;
}
if (is_dual_mipi_panel(hisifd)) {
val |= PDP_DSI1_EN_CLK_CFG;
if (is_ifbc_panel(hisifd)) {
set_reg(dss_base + DSS_GLB_PXL0_DIV, 0xb, 4, 0);
} else {
set_reg(dss_base + DSS_GLB_PXL0_DIV, 0x9, 4, 0);
}
}
if (is_ifbc_panel(hisifd)) {
val |= PDP_IFBC_EN_CLK_CFG;
}
outp32(dss_base + DSS_GLB_EN_CLK_CFG, val);
}
up(&hisi_fb_dss_panel_clk_sem);
}
static int dpe_off(struct platform_device *pdev)
{
int ret = 0;
struct k3_fb_data_type *k3fd = NULL;
BUG_ON(pdev == NULL);
k3fd = platform_get_drvdata(pdev);
BUG_ON(k3fd == NULL);
K3_FB_DEBUG("fb%d, +.\n", k3fd->index);
if (k3fd->panel_info.vsync_ctrl_type == VSYNC_CTRL_NONE) {
dpe_interrupt_mask(k3fd);
dpe_irq_disable(k3fd);
} else {
if (k3fd->vsync_ctrl.vsync_ctrl_enabled == 1) {
if (k3fd->panel_info.vsync_ctrl_type & VSYNC_CTRL_ISR_OFF) {
dpe_interrupt_mask(k3fd);
dpe_irq_disable(k3fd);
K3_FB_INFO("fb%d, need to disable dpe irq! vsync_ctrl_enabled=%d.\n",
k3fd->index, k3fd->vsync_ctrl.vsync_ctrl_enabled);
}
}
}
ret = panel_next_off(pdev);
dpe_deinit(k3fd);
dpe_regulator_disable(k3fd);
if (k3fd->index != PRIMARY_PANEL_IDX) {
if (k3fd_list[PRIMARY_PANEL_IDX] &&
(k3fd_list[PRIMARY_PANEL_IDX]->panel_info.vsync_ctrl_type & VSYNC_CTRL_CLK_OFF)) {
K3_FB_DEBUG("fb%d, pdp clk disable!\n", k3fd->index);
dpe_clk_disable(k3fd_list[PRIMARY_PANEL_IDX]);
}
}
/* reset DSI */
if (is_mipi_panel(k3fd)) {
if (is_dual_mipi_panel(k3fd)) {
outp32(k3fd->crgperi_base + PERRSTEN3_OFFSET, 0x00030000);
} else {
outp32(k3fd->crgperi_base + PERRSTEN3_OFFSET, 0x00020000);
}
}
K3_FB_DEBUG("fb%d, -.\n", k3fd->index);
return ret;
}
void disable_clk_panel(struct hisi_fb_data_type *hisifd)
{
char __iomem *dss_base = NULL;
uint32_t val = 0;
int new_refcount = 0;
BUG_ON(hisifd == NULL);
dss_base = hisifd->dss_base;
down(&hisi_fb_dss_panel_clk_sem);
new_refcount = --panel_refcount;
WARN_ON(new_refcount < 0);
if (!new_refcount) {
/* disable clk */
val = 0x0;
if (is_mipi_panel(hisifd)) {
val |= PDP_DSI0_DIS_CLK_CFG;
}
if (is_dual_mipi_panel(hisifd)) {
val |= PDP_DSI1_DIS_CLK_CFG;
}
if (is_ifbc_panel(hisifd)) {
val |= PDP_IFBC_DIS_CLK_CFG;
}
outp32(dss_base + DSS_GLB_DIS_CLK_CFG, val);
/* reset status */
val = 0x0;
if (is_mipi_panel(hisifd)) {
val |= PDP_DSI0_EN_RST_CFG;
}
if (is_dual_mipi_panel(hisifd)) {
val |= PDP_DSI1_EN_RST_CFG;
}
outp32(dss_base + DSS_GLB_EN_RST_CFG, val);
}
up(&hisi_fb_dss_panel_clk_sem);
}
