/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different. *This function scans which Riser Card being used(QSGMII or SGMII Riser Card), *then set the correct PHY address */ void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port, unsigned int port_num, int phy_base_addr) { unsigned int regnum = 0; int qsgmii; int i; int phy_real_addr; qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum); if (!qsgmii) return; for (i = base_port; i < base_port + port_num; i++) { if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) { phy_real_addr = phy_base_addr + i - base_port; fm_info_set_phy_address(i, phy_real_addr); } } }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; struct mii_dev *bus; int qsgmii; int phy_real_addr; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int srds_prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; printf("Initializing Fman\n"); initialize_lane_to_slot(); /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); memset(mdio_mux, 0, sizeof(mdio_mux)); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_tgec_mdio_init(bis, &tgec_mdio_info); /* Register the three virtual MDIO front-ends */ super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_RGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM1_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM2_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM3_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, "SUPER_HYDRA_FM1_TGEC_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, "SUPER_HYDRA_FM2_TGEC_MDIO"); /* * Program the DTSEC PHY addresses assuming that they are all SGMII. * For any DTSEC that's RGMII, we'll override its PHY address later. * We assume that DTSEC5 is only used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); #if (CONFIG_SYS_NUM_FMAN == 2) fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); #endif switch (srds_prtcl) { case 0: case 3: case 4: case 6: case 0x11: case 0x2a: case 0x34: case 0x36: fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); break; case 1: case 2: case 5: case 7: case 0x35: fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); break; default: printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); switch (slot) { case 1: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | BRDCFG1_EMI1_EN; break; case 2: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | BRDCFG1_EMI1_EN; break; case 3: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | BRDCFG1_EMI1_EN; break; case 5: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | BRDCFG1_EMI1_EN; break; case 6: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | BRDCFG1_EMI1_EN; break; case 7: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | BRDCFG1_EMI1_EN; break; }; super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the * second on-board RGMII port. The other DTSECs cannot * be routed to RGMII. */ debug("FM1@DTSEC%u is RGMII at address %u\n", idx + 1, 0); fm_info_set_phy_address(i, 0); mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN; super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"); qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); if (qsgmii) { for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) { if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) { phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1; fm_info_set_phy_address(i, phy_real_addr); } } switch (srds_prtcl) { case 0x00: case 0x03: case 0x04: case 0x06: case 0x11: case 0x2a: case 0x34: case 0x36: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3); break; case 0x01: case 0x02: case 0x05: case 0x07: case 0x35: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); break; default: break; } } /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the * need for Linux to do any muxing. This works because of the way * BRDCFG1 is defined, but it's a bit hackish. * * The PHY address for the XAUI card depends on which slot it's in. The * macros we use imply that the PHY address is based on which FM, but * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, * and FM2 could only use a XAUI in slot 4. On the Hydra board, we * check the actual slot and just use the macros as-is, even though * the P3041 and P5020 only have one Fman. */ lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } fm_info_set_mdio(FM1_10GEC1, miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); #if (CONFIG_SYS_NUM_FMAN == 2) for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { int idx = i - FM2_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; debug("FM2@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); switch (slot) { case 1: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | BRDCFG1_EMI1_EN; break; case 2: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | BRDCFG1_EMI1_EN; break; case 3: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | BRDCFG1_EMI1_EN; break; case 5: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | BRDCFG1_EMI1_EN; break; case 6: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | BRDCFG1_EMI1_EN; break; case 7: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | BRDCFG1_EMI1_EN; break; }; if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { super_hydra_mdio_set_mux( "SUPER_HYDRA_FM3_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name( "SUPER_HYDRA_FM3_SGMII_MDIO")); } else { super_hydra_mdio_set_mux( "SUPER_HYDRA_FM2_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name( "SUPER_HYDRA_FM2_SGMII_MDIO")); } break; case PHY_INTERFACE_MODE_RGMII: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the * second on-board RGMII port. The other DTSECs cannot * be routed to RGMII. */ debug("FM2@DTSEC%u is RGMII at address %u\n", idx + 1, 1); fm_info_set_phy_address(i, 1); mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN; super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman2: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"); set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR); bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO"); set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR); /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the * need for Linux to do any muxing. This works because of the way * BRDCFG1 is defined, but it's a bit hackish. * * The PHY address for the XAUI card depends on which slot it's in. The * macros we use imply that the PHY address is based on which FM, but * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, * and FM2 could only use a XAUI in slot 4. On the Hydra board, we * check the actual slot and just use the macros as-is, even though * the P3041 and P5020 only have one Fman. */ lane = serdes_get_first_lane(XAUI_FM2); if (lane >= 0) { debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } fm_info_set_mdio(FM2_10GEC1, miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); #endif cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; struct memac_mdio_info tg_memac_mdio_info; unsigned int i; unsigned int serdes1_prtcl, serdes2_prtcl; int qsgmii; struct mii_dev *bus; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); serdes1_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; if (!serdes1_prtcl) { printf("SERDES1 is not enabled\n"); return 0; } serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); serdes2_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; if (!serdes2_prtcl) { printf("SERDES2 is not enabled\n"); return 0; } serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); printf("Initializing Fman\n"); initialize_lane_to_slot(); memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); tg_memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_memac_mdio_init(bis, &tg_memac_mdio_info); /* * Program the two on board DTSEC PHY addresses assuming that they are * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and * 6 to on board SGMII phys */ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); switch (serdes1_prtcl) { case 0x29: case 0x2a: /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n", CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #ifdef CONFIG_ARCH_B4420 case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n", CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); /* Fixing Serdes clock by programming FPGA register */ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #endif default: printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n", serdes1_prtcl); break; } switch (serdes2_prtcl) { case 0x17: case 0x18: debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); break; case 0x48: case 0x49: debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); break; case 0xb1: case 0xb2: case 0x8c: case 0x8d: debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); /* * XFI does not need a PHY to work, but to make U-Boot * happy, assign a fake PHY address for a XFI port. */ fm_info_set_phy_address(FM1_10GEC1, 0); fm_info_set_phy_address(FM1_10GEC2, 1); break; case 0x98: /* XAUI in Slot1 and Slot2 */ debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n", CONFIG_SYS_FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); break; case 0x9E: /* XAUI in Slot2 */ debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); break; default: printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); break; } /*set PHY address for QSGMII Riser Card on slot2*/ bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM); if (qsgmii) { switch (serdes2_prtcl) { case 0xb2: case 0x8d: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); break; default: break; } } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { int idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: fm_info_set_mdio(i, miiphy_get_dev_by_name (DEFAULT_FM_TGEC_MDIO_NAME)); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: TGEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } cpu_eth_init(bis); #endif return pci_eth_init(bis); }