/* Reads the ID CODE out of the FPGA
* When the state machine is reset, the sequence 0, 1, 0, 0 will move
* it to a point where continually reading the TDO line will yield the
* ID code.
*
* This is because by default, the reset command loads the chip's ID
* into the data register, so all we have to do is read it out.
*/
static uint32_t jtag_idcode(struct jtag_state *state) {
int i;
uint32_t val = 0;
/* Reset the state machine */
jtag_reset(state);
/* Get into "Run-Test/ Idle" state */
gpio_set_value(state->tms, 0);
jtag_tick(state);
/* Get into "Select DR-Scan" state */
gpio_set_value(state->tms, 1);
jtag_tick(state);
/* Get into "Capture DR" state */
gpio_set_value(state->tms, 0);
jtag_tick(state);
/* Get into "Shift-DR" state */
gpio_set_value(state->tms, 0);
jtag_tick(state);
/* Read the code out */
for (i=0; i<32; i++) {
int ret = gpio_get_value(state->tdi);
val |= (ret<<i);
jtag_tick(state);
}
return val;
}
/* Send five 1s through JTAG, which will bring it into reset state */
static int jtag_reset(struct jtag_state *state) {
int i;
for (i=0; i<5; i++) {
gpio_set_value(state->tms, 1);
jtag_tick(state);
}
return 0;
}
int jtag_io(unsigned count, unsigned tms, unsigned tdi, unsigned *tdo) {
unsigned n = 0;
unsigned bit = 0;
while (count > 0) {
n |= (jtag_tick(tms & 1, tdi & 1) << bit);
bit++;
count--;
tms >>= 1;
tdi >>= 1;
}
*tdo = n;
return 0;
}
