/* manually trigger a new snapshot to be collected */
static ssize_t trigger_store(struct kgsl_device *device, const char *buf,
size_t count)
{
if (device && count > 0) {
mutex_lock(&device->mutex);
kgsl_device_snapshot(device, 0);
mutex_unlock(&device->mutex);
}
return count;
}
/**
* _ringbuffer_bootstrap_ucode() - Bootstrap GPU Ucode
* @rb: Pointer to adreno ringbuffer
* @load_jt: If non zero only load Jump tables
*
* Bootstrap ucode for GPU
* load_jt == 0, bootstrap full microcode
* load_jt == 1, bootstrap jump tables of microcode
*
* For example a bootstrap packet would like below
* Setup a type3 bootstrap packet
* PFP size to bootstrap
* PFP addr to write the PFP data
* PM4 size to bootstrap
* PM4 addr to write the PM4 data
* PFP dwords from microcode to bootstrap
* PM4 size dwords from microcode to bootstrap
*/
static int _ringbuffer_bootstrap_ucode(struct adreno_ringbuffer *rb,
unsigned int load_jt)
{
unsigned int *cmds, bootstrap_size;
int i = 0;
int ret;
struct kgsl_device *device = rb->device;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
unsigned int pm4_size, pm4_idx, pm4_addr, pfp_size, pfp_idx, pfp_addr;
/* Only bootstrap jump tables of ucode */
if (load_jt) {
pm4_idx = adreno_dev->gpucore->pm4_jt_idx;
pm4_addr = adreno_dev->gpucore->pm4_jt_addr;
pfp_idx = adreno_dev->gpucore->pfp_jt_idx;
pfp_addr = adreno_dev->gpucore->pfp_jt_addr;
} else {
/* Bootstrap full ucode */
pm4_idx = 1;
pm4_addr = 0;
pfp_idx = 1;
pfp_addr = 0;
}
pm4_size = (adreno_dev->pm4_fw_size - pm4_idx);
pfp_size = (adreno_dev->pfp_fw_size - pfp_idx);
/*
* Overwrite the first entry in the jump table with the special
* bootstrap opcode
*/
if (adreno_is_a4xx(adreno_dev)) {
adreno_writereg(adreno_dev, ADRENO_REG_CP_PFP_UCODE_ADDR,
0x400);
adreno_writereg(adreno_dev, ADRENO_REG_CP_PFP_UCODE_DATA,
0x6f0009);
bootstrap_size = (pm4_size + pfp_size + 5 + 6);
} else {
adreno_writereg(adreno_dev, ADRENO_REG_CP_PFP_UCODE_ADDR,
0x200);
adreno_writereg(adreno_dev, ADRENO_REG_CP_PFP_UCODE_DATA,
0x6f0005);
bootstrap_size = (pm4_size + pfp_size + 5);
}
/* clear ME_HALT to start micro engine */
adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, 0);
cmds = adreno_ringbuffer_allocspace(rb, bootstrap_size);
if (IS_ERR(cmds))
return PTR_ERR(cmds);
if (cmds == NULL)
return -ENOSPC;
/* Construct the packet that bootsraps the ucode */
*cmds++ = cp_type3_packet(CP_BOOTSTRAP_UCODE, (bootstrap_size - 1));
*cmds++ = pfp_size;
*cmds++ = pfp_addr;
*cmds++ = pm4_size;
*cmds++ = pm4_addr;
/**
* Theory of operation:
*
* In A4x, we cannot have the PFP executing instructions while its instruction
* RAM is loading. We load the PFP's instruction RAM using type-0 writes
* from the ME.
*
* To make sure the PFP is not fetching instructions at the same time,
* we put it in a one-instruction loop:
* mvc (ME), (ringbuffer)
* which executes repeatedly until all of the data has been moved from
* the ring buffer to the ME.
*/
if (adreno_is_a4xx(adreno_dev)) {
for (i = pm4_idx; i < adreno_dev->pm4_fw_size; i++)
*cmds++ = adreno_dev->pm4_fw[i];
for (i = pfp_idx; i < adreno_dev->pfp_fw_size; i++)
*cmds++ = adreno_dev->pfp_fw[i];
*cmds++ = cp_type3_packet(CP_REG_RMW, 3);
*cmds++ = 0x20000000 + A4XX_CP_RB_WPTR;
*cmds++ = 0xffffffff;
*cmds++ = 0x00000002;
*cmds++ = cp_type3_packet(CP_INTERRUPT, 1);
*cmds++ = 0;
rb->wptr = rb->wptr - 2;
adreno_ringbuffer_submit(rb, NULL);
rb->wptr = rb->wptr + 2;
} else {
for (i = pfp_idx; i < adreno_dev->pfp_fw_size; i++)
*cmds++ = adreno_dev->pfp_fw[i];
for (i = pm4_idx; i < adreno_dev->pm4_fw_size; i++)
*cmds++ = adreno_dev->pm4_fw[i];
adreno_ringbuffer_submit(rb, NULL);
}
/* idle device to validate bootstrap */
ret = adreno_spin_idle(device);
if (ret) {
KGSL_DRV_ERR(rb->device,
"microcode bootstrap failed to idle\n");
kgsl_device_snapshot(device, NULL);
}
return ret;
}
