static void a2xx_ctxt_restore(struct adreno_device *adreno_dev,
struct adreno_context *context)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int cmds[5];
if (context == NULL) {
/* No context - set the default apgetable and thats it */
kgsl_mmu_setstate(device, device->mmu.defaultpagetable);
return;
}
KGSL_CTXT_INFO(device, "context flags %08x\n", context->flags);
cmds[0] = cp_nop_packet(1);
cmds[1] = KGSL_CONTEXT_TO_MEM_IDENTIFIER;
cmds[2] = cp_type3_packet(CP_MEM_WRITE, 2);
cmds[3] = device->memstore.gpuaddr +
KGSL_DEVICE_MEMSTORE_OFFSET(current_context);
cmds[4] = (unsigned int) context;
adreno_ringbuffer_issuecmds(device, 0, cmds, 5);
kgsl_mmu_setstate(device, context->pagetable);
#ifndef CONFIG_MSM_KGSL_CFF_DUMP_NO_CONTEXT_MEM_DUMP
kgsl_cffdump_syncmem(NULL, &context->gpustate,
context->gpustate.gpuaddr, LCC_SHADOW_SIZE +
REG_SHADOW_SIZE + CMD_BUFFER_SIZE + TEX_SHADOW_SIZE, false);
#endif
/* restore gmem.
* (note: changes shader. shader must not already be restored.)
*/
if (context->flags & CTXT_FLAGS_GMEM_RESTORE) {
adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
context->context_gmem_shadow.gmem_restore, 3);
/* Restore TP0_CHICKEN */
adreno_ringbuffer_issuecmds(device, 0,
context->chicken_restore, 3);
context->flags &= ~CTXT_FLAGS_GMEM_RESTORE;
}
/* restore registers and constants. */
adreno_ringbuffer_issuecmds(device, 0,
context->reg_restore, 3);
/* restore shader instructions & partitioning. */
if (context->flags & CTXT_FLAGS_SHADER_RESTORE) {
adreno_ringbuffer_issuecmds(device, 0,
context->shader_restore, 3);
}
if (adreno_is_a20x(adreno_dev)) {
cmds[0] = cp_type3_packet(CP_SET_BIN_BASE_OFFSET, 1);
cmds[1] = context->bin_base_offset;
adreno_ringbuffer_issuecmds(device, 0, cmds, 2);
}
}
int adreno_drawctxt_switch(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt,
unsigned int flags)
{
struct kgsl_device *device = &adreno_dev->dev;
int ret = 0;
/* already current? */
if (adreno_dev->drawctxt_active == drawctxt)
return ret;
trace_adreno_drawctxt_switch(adreno_dev->drawctxt_active,
drawctxt, flags);
/* Get a refcount to the new instance */
if (drawctxt) {
if (!_kgsl_context_get(&drawctxt->base))
return -EINVAL;
ret = kgsl_mmu_setstate(&device->mmu,
drawctxt->base.proc_priv->pagetable,
adreno_dev->drawctxt_active ?
adreno_dev->drawctxt_active->base.id :
KGSL_CONTEXT_INVALID);
/* Set the new context */
ret = adreno_context_restore(adreno_dev, drawctxt);
if (ret) {
KGSL_DRV_ERR(device,
"Error in GPU context %d restore: %d\n",
drawctxt->base.id, ret);
return ret;
}
} else {
/*
* No context - set the default pagetable and thats it.
* If there isn't a current context, the kgsl_mmu_setstate
* will use the CPU path so we don't need to give
* it a valid context id.
*/
ret = kgsl_mmu_setstate(&device->mmu,
device->mmu.defaultpagetable,
adreno_dev->drawctxt_active->base.id);
}
/* Put the old instance of the active drawctxt */
if (adreno_dev->drawctxt_active)
kgsl_context_put(&adreno_dev->drawctxt_active->base);
adreno_dev->drawctxt_active = drawctxt;
return 0;
}
int
kgsl_g12_cmdstream_issueibcmds(struct kgsl_device *device,
struct kgsl_pagetable *pagetable,
int drawctxt_index,
uint32_t ibaddr,
int sizedwords,
int *timestamp,
unsigned int ctrl)
{
unsigned int ofs = PACKETSIZE_STATESTREAM * sizeof(unsigned int);
unsigned int cnt = 5;
unsigned int nextbuf = (g_z1xx.curr + 1) % GSL_HAL_NUMCMDBUFFERS;
unsigned int nextaddr = g_z1xx.cmdbufdesc[nextbuf].physaddr;
unsigned int nextcnt = 0x9000 | 5;
struct kgsl_memdesc tmp = {0};
unsigned int cmd;
cmd = ibaddr;
tmp.hostptr = (void *)*timestamp;
/* context switch */
if (drawctxt_index != (int)g_z1xx.prevctx) {
kgsl_mmu_setstate(device, pagetable);
cnt = PACKETSIZE_STATESTREAM;
ofs = 0;
} else {
kgsl_setstate(device, device->mmu.tlb_flags);
}
device->current_timestamp++;
*timestamp = device->current_timestamp;
g_z1xx.prevctx = drawctxt_index;
g_z1xx.offs = 10;
beginpacket(&g_z1xx, cmd + ofs, cnt);
tmp.hostptr = (void *)(tmp.hostptr +
(sizedwords * sizeof(unsigned int)));
tmp.size = 12;
kgsl_sharedmem_writel(&tmp, 4, nextaddr);
kgsl_sharedmem_writel(&tmp, 8, nextcnt);
/* sync mem */
kgsl_sharedmem_write((const struct kgsl_memdesc *)
&g_z1xx.cmdbufdesc[g_z1xx.curr], 0,
g_z1xx.cmdbuf[g_z1xx.curr],
(512 + 13) * sizeof(unsigned int));
g_z1xx.offs = 0;
g_z1xx.curr = nextbuf;
kgsl_g12_cmdwindow_write(device,
KGSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, ctrl);
kgsl_g12_cmdwindow_write(device,
KGSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
return KGSL_SUCCESS;
}
int
kgsl_g12_cmdstream_issueibcmds(struct kgsl_device_private *dev_priv,
int drawctxt_index,
uint32_t ibaddr,
int sizedwords,
uint32_t *timestamp,
unsigned int ctrl)
{
unsigned int result = 0;
unsigned int ofs = PACKETSIZE_STATESTREAM * sizeof(unsigned int);
unsigned int cnt = 5;
unsigned int nextaddr = 0;
unsigned int index = 0;
unsigned int nextcnt = 0x9000 | 5;
struct kgsl_memdesc tmp = {0};
unsigned int cmd;
struct kgsl_device *device = dev_priv->device;
struct kgsl_pagetable *pagetable = dev_priv->process_priv->pagetable;
struct kgsl_g12_device *g12_device = (struct kgsl_g12_device *) device;
cmd = ibaddr;
tmp.hostptr = (void *)*timestamp;
KGSL_CMD_INFO("ctxt %d ibaddr 0x%08x sizedwords %d",
drawctxt_index, ibaddr, sizedwords);
if (drawctxt_index != (int)g_z1xx.prevctx) {
kgsl_mmu_setstate(device, pagetable);
cnt = PACKETSIZE_STATESTREAM;
ofs = 0;
} else {
kgsl_g12_setstate(device, device->mmu.tlb_flags);
}
result = wait_event_interruptible_timeout(g12_device->wait_timestamp_wq,
room_in_rb(g12_device),
msecs_to_jiffies(KGSL_TIMEOUT_DEFAULT));
if (result < 0) {
KGSL_CMD_ERR("failed waiting for ringbuffer. result %d",
result);
goto error;
}
result = 0;
index = g12_device->current_timestamp % KGSL_G12_PACKET_COUNT;
g12_device->current_timestamp++;
*timestamp = g12_device->current_timestamp;
g_z1xx.prevctx = drawctxt_index;
addcmd(&g_z1xx, index, cmd + ofs, cnt);
nextaddr = g_z1xx.cmdbufdesc.physaddr
+ rb_offset((index + 1) % KGSL_G12_PACKET_COUNT);
tmp.hostptr = (void *)(tmp.hostptr +
(sizedwords * sizeof(unsigned int)));
tmp.size = 12;
kgsl_sharedmem_writel(&tmp, 4, nextaddr);
kgsl_sharedmem_writel(&tmp, 8, nextcnt);
kgsl_g12_cmdwindow_write(device,
KGSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 1);
kgsl_g12_cmdwindow_write(device,
KGSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
error:
return result;
}
int
kgsl_g12_cmdstream_issueibcmds(struct kgsl_device_private *dev_priv,
int drawctxt_index,
uint32_t ibaddr,
int sizedwords,
uint32_t *timestamp,
unsigned int ctrl)
{
unsigned int result = 0;
unsigned int ofs = PACKETSIZE_STATESTREAM * sizeof(unsigned int);
unsigned int cnt = 5;
unsigned int nextaddr = 0;
unsigned int index = 0;
unsigned int nextindex;
unsigned int nextcnt = KGSL_G12_STREAM_END_CMD | 5;
struct kgsl_memdesc tmp = {0};
unsigned int cmd;
struct kgsl_device *device = dev_priv->device;
struct kgsl_pagetable *pagetable = dev_priv->process_priv->pagetable;
struct kgsl_g12_device *g12_device = (struct kgsl_g12_device *) device;
cmd = ibaddr;
tmp.hostptr = (void *)*timestamp;
KGSL_CMD_INFO("ctxt %d ibaddr 0x%08x sizedwords %d",
drawctxt_index, ibaddr, sizedwords);
/* context switch */
if (drawctxt_index != (int)g12_device->ringbuffer.prevctx) {
KGSL_CMD_INFO("context switch %d -> %d",
drawctxt_index, g12_device->ringbuffer.prevctx);
kgsl_mmu_setstate(device, pagetable);
cnt = PACKETSIZE_STATESTREAM;
ofs = 0;
}
kgsl_g12_setstate(device, kgsl_pt_get_flags(device->mmu.hwpagetable,
device->id));
result = wait_event_interruptible_timeout(g12_device->wait_timestamp_wq,
room_in_rb(g12_device),
msecs_to_jiffies(KGSL_TIMEOUT_DEFAULT));
if (result < 0) {
KGSL_CMD_ERR("failed waiting for ringbuffer. result %d",
result);
goto error;
}
result = 0;
index = g12_device->current_timestamp % KGSL_G12_PACKET_COUNT;
g12_device->current_timestamp++;
nextindex = g12_device->current_timestamp % KGSL_G12_PACKET_COUNT;
*timestamp = g12_device->current_timestamp;
g12_device->ringbuffer.prevctx = drawctxt_index;
addcmd(&g12_device->ringbuffer, index, cmd + ofs, cnt);
/* Make sure the next ringbuffer entry has a marker */
addmarker(&g12_device->ringbuffer, nextindex);
nextaddr = g12_device->ringbuffer.cmdbufdesc.gpuaddr
+ rb_offset(nextindex);
tmp.hostptr = (void *)(tmp.hostptr +
(sizedwords * sizeof(unsigned int)));
tmp.size = 12;
kgsl_sharedmem_writel(&tmp, 4, nextaddr);
kgsl_sharedmem_writel(&tmp, 8, nextcnt);
cmd = (int)(((2) & VGV3_CONTROL_MARKADD_FMASK)
<< VGV3_CONTROL_MARKADD_FSHIFT);
kgsl_g12_cmdwindow_write(device,
KGSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, cmd);
kgsl_g12_cmdwindow_write(device,
KGSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
error:
return result;
}
int
kgsl_g12_cmdstream_issueibcmds(struct kgsl_device_private *dev_priv,
struct kgsl_context *context,
struct kgsl_ibdesc *ibdesc,
unsigned int numibs,
uint32_t *timestamp,
unsigned int ctrl)
{
int result = 0;
unsigned int ofs = PACKETSIZE_STATESTREAM * sizeof(unsigned int);
unsigned int cnt = 5;
unsigned int nextaddr = 0;
unsigned int index = 0;
unsigned int nextindex;
unsigned int nextcnt = KGSL_G12_STREAM_END_CMD | 5;
struct kgsl_memdesc tmp = {0};
unsigned int cmd;
struct kgsl_device *device = dev_priv->device;
struct kgsl_pagetable *pagetable = dev_priv->process_priv->pagetable;
struct kgsl_g12_device *g12_device = KGSL_G12_DEVICE(device);
unsigned int sizedwords;
if (device->state & KGSL_STATE_HUNG) {
return -EINVAL;
goto error;
}
if (numibs != 1) {
KGSL_DRV_ERR(device, "Invalid number of ibs: %d\n", numibs);
result = -EINVAL;
goto error;
}
cmd = ibdesc[0].gpuaddr;
sizedwords = ibdesc[0].sizedwords;
tmp.hostptr = (void *)*timestamp;
KGSL_CMD_INFO(device, "ctxt %d ibaddr 0x%08x sizedwords %d\n",
context->id, cmd, sizedwords);
/* context switch */
if ((context->id != (int)g12_device->ringbuffer.prevctx) ||
(ctrl & KGSL_CONTEXT_CTX_SWITCH)) {
KGSL_CMD_INFO(device, "context switch %d -> %d\n",
context->id, g12_device->ringbuffer.prevctx);
kgsl_mmu_setstate(device, pagetable);
cnt = PACKETSIZE_STATESTREAM;
ofs = 0;
}
kgsl_g12_setstate(device, kgsl_pt_get_flags(device->mmu.hwpagetable,
device->id));
result = wait_event_interruptible_timeout(device->wait_queue,
room_in_rb(g12_device),
msecs_to_jiffies(KGSL_TIMEOUT_DEFAULT));
if (result <= 0) {
KGSL_CMD_ERR(device, "wait_event_interruptible_timeout "
"failed: %d\n", result);
goto error;
}
result = 0;
index = g12_device->current_timestamp % KGSL_G12_PACKET_COUNT;
g12_device->current_timestamp++;
nextindex = g12_device->current_timestamp % KGSL_G12_PACKET_COUNT;
*timestamp = g12_device->current_timestamp;
g12_device->ringbuffer.prevctx = context->id;
addcmd(&g12_device->ringbuffer, index, cmd + ofs, cnt);
/* Make sure the next ringbuffer entry has a marker */
addmarker(&g12_device->ringbuffer, nextindex);
nextaddr = g12_device->ringbuffer.cmdbufdesc.gpuaddr
+ rb_offset(nextindex);
tmp.hostptr = (void *)(tmp.hostptr +
(sizedwords * sizeof(unsigned int)));
tmp.size = 12;
kgsl_sharedmem_writel(&tmp, 4, nextaddr);
kgsl_sharedmem_writel(&tmp, 8, nextcnt);
/* sync memory before activating the hardware for the new command*/
mb();
cmd = (int)(((2) & VGV3_CONTROL_MARKADD_FMASK)
<< VGV3_CONTROL_MARKADD_FSHIFT);
kgsl_g12_cmdwindow_write(device,
KGSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, cmd);
kgsl_g12_cmdwindow_write(device,
KGSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
error:
return result;
}
/* switch drawing contexts */
void
adreno_drawctxt_switch(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt,
unsigned int flags)
{
struct adreno_context *active_ctxt =
adreno_dev->drawctxt_active;
struct kgsl_device *device = &adreno_dev->dev;
unsigned int cmds[5];
if (drawctxt) {
if (flags & KGSL_CONTEXT_SAVE_GMEM)
/* Set the flag in context so that the save is done
* when this context is switched out. */
drawctxt->flags |= CTXT_FLAGS_GMEM_SAVE;
else
/* Remove GMEM saving flag from the context */
drawctxt->flags &= ~CTXT_FLAGS_GMEM_SAVE;
}
/* already current? */
if (active_ctxt == drawctxt)
return;
KGSL_CTXT_INFO(device, "from %p to %p flags %d\n",
adreno_dev->drawctxt_active, drawctxt, flags);
/* save old context*/
if (active_ctxt && active_ctxt->flags & CTXT_FLAGS_GPU_HANG)
KGSL_CTXT_WARN(device,
"Current active context has caused gpu hang\n");
if (active_ctxt != NULL) {
KGSL_CTXT_INFO(device,
"active_ctxt flags %08x\n", active_ctxt->flags);
/* save registers and constants. */
adreno_ringbuffer_issuecmds(device, 0,
active_ctxt->reg_save, 3);
if (active_ctxt->flags & CTXT_FLAGS_SHADER_SAVE) {
/* save shader partitioning and instructions. */
adreno_ringbuffer_issuecmds(device,
KGSL_CMD_FLAGS_PMODE,
active_ctxt->shader_save, 3);
/* fixup shader partitioning parameter for
* SET_SHADER_BASES.
*/
adreno_ringbuffer_issuecmds(device, 0,
active_ctxt->shader_fixup, 3);
active_ctxt->flags |= CTXT_FLAGS_SHADER_RESTORE;
}
if (active_ctxt->flags & CTXT_FLAGS_GMEM_SAVE
&& active_ctxt->flags & CTXT_FLAGS_GMEM_SHADOW) {
/* save gmem.
* (note: changes shader. shader must already be saved.)
*/
adreno_ringbuffer_issuecmds(device,
KGSL_CMD_FLAGS_PMODE,
active_ctxt->context_gmem_shadow.gmem_save, 3);
/* Restore TP0_CHICKEN */
adreno_ringbuffer_issuecmds(device, 0,
active_ctxt->chicken_restore, 3);
active_ctxt->flags |= CTXT_FLAGS_GMEM_RESTORE;
}
}
adreno_dev->drawctxt_active = drawctxt;
/* restore new context */
if (drawctxt != NULL) {
KGSL_CTXT_INFO(device,
"drawctxt flags %08x\n", drawctxt->flags);
cmds[0] = pm4_nop_packet(1);
cmds[1] = KGSL_CONTEXT_TO_MEM_IDENTIFIER;
cmds[2] = pm4_type3_packet(PM4_MEM_WRITE, 2);
cmds[3] = device->memstore.gpuaddr +
KGSL_DEVICE_MEMSTORE_OFFSET(current_context);
cmds[4] = (unsigned int)adreno_dev->drawctxt_active;
adreno_ringbuffer_issuecmds(device, 0, cmds, 5);
kgsl_mmu_setstate(device, drawctxt->pagetable);
#ifndef CONFIG_MSM_KGSL_CFF_DUMP_NO_CONTEXT_MEM_DUMP
kgsl_cffdump_syncmem(NULL, &drawctxt->gpustate,
drawctxt->gpustate.gpuaddr, LCC_SHADOW_SIZE +
REG_SHADOW_SIZE + CMD_BUFFER_SIZE + TEX_SHADOW_SIZE,
false);
#endif
/* restore gmem.
* (note: changes shader. shader must not already be restored.)
*/
if (drawctxt->flags & CTXT_FLAGS_GMEM_RESTORE) {
adreno_ringbuffer_issuecmds(device,
KGSL_CMD_FLAGS_PMODE,
drawctxt->context_gmem_shadow.gmem_restore, 3);
/* Restore TP0_CHICKEN */
adreno_ringbuffer_issuecmds(device, 0,
drawctxt->chicken_restore, 3);
drawctxt->flags &= ~CTXT_FLAGS_GMEM_RESTORE;
}
/* restore registers and constants. */
adreno_ringbuffer_issuecmds(device, 0,
drawctxt->reg_restore, 3);
/* restore shader instructions & partitioning. */
if (drawctxt->flags & CTXT_FLAGS_SHADER_RESTORE) {
adreno_ringbuffer_issuecmds(device, 0,
drawctxt->shader_restore, 3);
}
cmds[0] = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1);
cmds[1] = drawctxt->bin_base_offset;
if (!adreno_is_a220(adreno_dev))
adreno_ringbuffer_issuecmds(device, 0, cmds, 2);
} else
kgsl_mmu_setstate(device, device->mmu.defaultpagetable);
}
int adreno_drawctxt_switch(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt,
unsigned int flags)
{
struct kgsl_device *device = &adreno_dev->dev;
int ret = 0;
if (drawctxt) {
if (flags & KGSL_CONTEXT_SAVE_GMEM)
set_bit(ADRENO_CONTEXT_GMEM_SAVE, &drawctxt->priv);
else
clear_bit(ADRENO_CONTEXT_GMEM_SAVE, &drawctxt->priv);
}
if (adreno_dev->drawctxt_active == drawctxt) {
if (drawctxt && drawctxt->ops->draw_workaround)
ret = drawctxt->ops->draw_workaround(adreno_dev,
drawctxt);
return ret;
}
trace_adreno_drawctxt_switch(adreno_dev->drawctxt_active,
drawctxt, flags);
if (adreno_dev->drawctxt_active) {
ret = context_save(adreno_dev, adreno_dev->drawctxt_active);
if (ret) {
KGSL_DRV_ERR(device,
"Error in GPU context %d save: %d\n",
adreno_dev->drawctxt_active->base.id, ret);
return ret;
}
}
if (drawctxt) {
if (!_kgsl_context_get(&drawctxt->base))
return -EINVAL;
ret = kgsl_mmu_setstate(&device->mmu,
drawctxt->base.proc_priv->pagetable,
adreno_dev->drawctxt_active ?
adreno_dev->drawctxt_active->base.id :
KGSL_CONTEXT_INVALID);
ret = drawctxt->ops->restore(adreno_dev, drawctxt);
if (ret) {
KGSL_DRV_ERR(device,
"Error in GPU context %d restore: %d\n",
drawctxt->base.id, ret);
return ret;
}
} else {
ret = kgsl_mmu_setstate(&device->mmu,
device->mmu.defaultpagetable,
adreno_dev->drawctxt_active->base.id);
}
if (adreno_dev->drawctxt_active)
kgsl_context_put(&adreno_dev->drawctxt_active->base);
adreno_dev->drawctxt_active = drawctxt;
return 0;
}
int adreno_drawctxt_switch(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt,
unsigned int flags)
{
struct kgsl_device *device = &adreno_dev->dev;
int ret = 0;
if (drawctxt) {
/*
* Handle legacy gmem / save restore flag on each IB.
* Userspace sets to guard IB sequences that require
* gmem to be saved and clears it at the end of the
* sequence.
*/
if (flags & KGSL_CONTEXT_SAVE_GMEM)
/* Set the flag in context so that the save is done
* when this context is switched out. */
set_bit(ADRENO_CONTEXT_GMEM_SAVE, &drawctxt->priv);
else
/* Remove GMEM saving flag from the context */
clear_bit(ADRENO_CONTEXT_GMEM_SAVE, &drawctxt->priv);
}
/* already current? */
if (adreno_dev->drawctxt_active == drawctxt) {
if (drawctxt && drawctxt->ops->draw_workaround)
ret = drawctxt->ops->draw_workaround(adreno_dev,
drawctxt);
return ret;
}
trace_adreno_drawctxt_switch(adreno_dev->drawctxt_active,
drawctxt, flags);
/* Get a refcount to the new instance */
if (drawctxt) {
if (!_kgsl_context_get(&drawctxt->base))
return -EINVAL;
ret = kgsl_mmu_setstate(&device->mmu,
drawctxt->base.proc_priv->pagetable,
adreno_dev->drawctxt_active ?
adreno_dev->drawctxt_active->base.id :
KGSL_CONTEXT_INVALID);
/* Set the new context */
ret = drawctxt->ops->restore(adreno_dev, drawctxt);
if (ret) {
KGSL_DRV_ERR(device,
"Error in GPU context %d restore: %d\n",
drawctxt->base.id, ret);
return ret;
}
} else {
/*
* No context - set the default pagetable and thats it.
* If there isn't a current context, the kgsl_mmu_setstate
* will use the CPU path so we don't need to give
* it a valid context id.
*/
ret = kgsl_mmu_setstate(&device->mmu,
device->mmu.defaultpagetable,
adreno_dev->drawctxt_active->base.id);
}
/* Put the old instance of the active drawctxt */
if (adreno_dev->drawctxt_active)
kgsl_context_put(&adreno_dev->drawctxt_active->base);
adreno_dev->drawctxt_active = drawctxt;
return 0;
}
static void a2xx_drawctxt_restore(struct adreno_device *adreno_dev,
struct adreno_context *context)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int cmds[5];
if (context == NULL) {
kgsl_mmu_setstate(&device->mmu, device->mmu.defaultpagetable,
adreno_dev->drawctxt_active->id);
return;
}
KGSL_CTXT_INFO(device, "context flags %08x\n", context->flags);
cmds[0] = cp_nop_packet(1);
cmds[1] = KGSL_CONTEXT_TO_MEM_IDENTIFIER;
cmds[2] = cp_type3_packet(CP_MEM_WRITE, 2);
cmds[3] = device->memstore.gpuaddr +
KGSL_MEMSTORE_OFFSET(KGSL_MEMSTORE_GLOBAL, current_context);
cmds[4] = context->id;
adreno_ringbuffer_issuecmds(device, context, KGSL_CMD_FLAGS_NONE,
cmds, 5);
kgsl_mmu_setstate(&device->mmu, context->pagetable, context->id);
#ifndef CONFIG_MSM_KGSL_CFF_DUMP_NO_CONTEXT_MEM_DUMP
kgsl_cffdump_syncmem(NULL, &context->gpustate,
context->gpustate.gpuaddr, LCC_SHADOW_SIZE +
REG_SHADOW_SIZE + CMD_BUFFER_SIZE + TEX_SHADOW_SIZE, false);
#endif
if (context->flags & CTXT_FLAGS_GMEM_RESTORE) {
adreno_ringbuffer_issuecmds(device, context,
KGSL_CMD_FLAGS_PMODE,
context->context_gmem_shadow.gmem_restore, 3);
if (!(context->flags & CTXT_FLAGS_PREAMBLE)) {
adreno_ringbuffer_issuecmds(device, context,
KGSL_CMD_FLAGS_NONE,
context->chicken_restore, 3);
}
context->flags &= ~CTXT_FLAGS_GMEM_RESTORE;
}
if (!(context->flags & CTXT_FLAGS_PREAMBLE)) {
adreno_ringbuffer_issuecmds(device, context,
KGSL_CMD_FLAGS_NONE, context->reg_restore, 3);
if (context->flags & CTXT_FLAGS_SHADER_RESTORE) {
adreno_ringbuffer_issuecmds(device, context,
KGSL_CMD_FLAGS_NONE,
context->shader_restore, 3);
}
}
if (adreno_is_a20x(adreno_dev)) {
cmds[0] = cp_type3_packet(CP_SET_BIN_BASE_OFFSET, 1);
cmds[1] = context->bin_base_offset;
adreno_ringbuffer_issuecmds(device, context,
KGSL_CMD_FLAGS_NONE, cmds, 2);
}
}