/* XXX: should be rewritten using bus_space_read_region? */
static void
z3rambd_altmem_strategy(void *aux, struct buf *bp)
{
struct z3rambd_softc *sc = aux;
void *addr;
size_t off, bpos;
int s;
bpos = 0;
bp->b_resid = bp->b_bcount;
off = bp->b_blkno << DEV_BSHIFT;
s = splbio();
addr = (char *)((char*)sc->sc_va + off);
#ifdef Z3RAMBD_DEBUG
aprint_normal_dev(sc->sc_dev,"stratetgy at %x %x\n", (bus_addr_t) addr,
(bus_addr_t) kvtop(addr));
#endif /* Z3RAMBD_DEBUG */
if (bp->b_flags & B_READ)
memcpy((char *)bp->b_data, addr, bp->b_resid);
else
memcpy(addr, (char *)bp->b_data, bp->b_resid);
splx(s);
}
hide void
mc_reset_rxdma(struct mc_softc *sc)
{
dbdma_command_t *cmd = sc->sc_rxdmacmd;
dbdma_regmap_t *dmareg = sc->sc_rxdma;
int i;
u_int8_t maccc;
/* Disable receiver, reset the DMA channels */
maccc = NIC_GET(sc, MACE_MACCC);
NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV);
dbdma_reset(dmareg);
for (i = 0; i < MC_RXDMABUFS; i++) {
DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, ETHERMTU + 22,
sc->sc_rxbuf_phys + MC_BUFSIZE * i, DBDMA_INT_ALWAYS,
DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
cmd++;
}
DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0,
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS);
out32rb(&cmd->d_cmddep, kvtop((void *)sc->sc_rxdmacmd));
cmd++;
dbdma_start(dmareg, sc->sc_rxdmacmd);
sc->sc_tail = 0;
/* Reenable receiver, reenable DMA */
NIC_PUT(sc, MACE_MACCC, maccc);
}
hide void
mc_reset_txdma(struct mc_softc *sc)
{
dbdma_command_t *cmd = sc->sc_txdmacmd;
dbdma_regmap_t *dmareg = sc->sc_txdma;
u_int8_t maccc;
/* disable transmitter */
maccc = NIC_GET(sc, MACE_MACCC);
NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT);
dbdma_reset(dmareg);
DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_phys,
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
cmd++;
DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0,
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
out32rb(&dmareg->d_cmdptrhi, 0);
out32rb(&dmareg->d_cmdptrlo, kvtop((void *)sc->sc_txdmacmd));
/* restore old value */
NIC_PUT(sc, MACE_MACCC, maccc);
}
/* ARGSUSED */
int
oabs(bsm_absolute_)(bus_space_tag_t tag, bus_addr_t address,
bus_size_t size, int flags, bus_space_handle_t *handlep)
{
uint32_t pa = kvtop((void*) tag->base);
*handlep = tag->base + (address - pa) * AMIGA_SIMPLE_BUS_STRIDE;
return 0;
}
void
frame_sanity_check(struct trapframe *tf, struct lwp *l)
{
extern int kernel_text;
extern int etext;
extern register_t kpsw;
extern vaddr_t hpt_base;
extern vsize_t hpt_mask;
vsize_t uspace_size;
#define SANITY(e) \
do { \
if (sanity_frame == NULL && !(e)) { \
sanity_frame = tf; \
sanity_lwp = l; \
sanity_checked = __LINE__; \
} \
} while (/* CONSTCOND */ 0)
SANITY((tf->tf_ipsw & kpsw) == kpsw);
SANITY(tf->tf_hptm == hpt_mask && tf->tf_vtop == hpt_base);
SANITY((kpsw & PSW_I) == 0 || tf->tf_eiem != 0);
if (tf->tf_iisq_head == HPPA_SID_KERNEL) {
/*
* If the trap happened in the gateway
* page, we take the easy way out and
* assume that the trapframe is okay.
*/
if ((tf->tf_iioq_head & ~PAGE_MASK) != SYSCALLGATE) {
SANITY(!USERMODE(tf->tf_iioq_head));
SANITY(!USERMODE(tf->tf_iioq_tail));
SANITY(tf->tf_iioq_head >= (u_int) &kernel_text);
SANITY(tf->tf_iioq_head < (u_int) &etext);
SANITY(tf->tf_iioq_tail >= (u_int) &kernel_text);
SANITY(tf->tf_iioq_tail < (u_int) &etext);
#ifdef HPPA_REDZONE
uspace_size = HPPA_REDZONE;
#else
uspace_size = USPACE;
#endif
SANITY(l == NULL ||
((tf->tf_sp >= (u_int)(l->l_addr) + PAGE_SIZE &&
tf->tf_sp < (u_int)(l->l_addr) + uspace_size)));
}
} else {
SANITY(USERMODE(tf->tf_iioq_head));
SANITY(USERMODE(tf->tf_iioq_tail));
SANITY(l != NULL && tf->tf_cr30 == kvtop((caddr_t)l->l_addr));
}
#undef SANITY
if (sanity_frame == tf) {
(void) trap_kdebug(T_IBREAK, 0, tf);
sanity_frame = NULL;
sanity_lwp = NULL;
sanity_checked = 0;
}
}
void
gencp_attach(struct gencp_softc *gsc)
{
aprint_normal(": generic clockport pa 0x%x\n",
(bus_addr_t) kvtop((void*) gsc->cpb_aa->cp_iot->base));
gsc->cpb_aa->cp_intr_establish = clockport_generic_intr_establish;
config_found(gsc->sc_dev, gsc->cpb_aa, 0);
}
void
le_isapnp_attach(struct device *parent, struct device *self, void *aux)
{
struct le_softc *lesc = (void *)self;
struct isa_attach_args *ia = aux;
struct am7990_softc *sc = &lesc->sc_am7990;
bus_space_tag_t iot = lesc->sc_iot;
bus_space_handle_t ioh = lesc->sc_ioh;
int i;
lesc->sc_iot = iot = ia->ia_iot;
lesc->sc_ioh = ioh = ia->ipa_io[0].h;
lesc->sc_rap = NE2100_RAP;
lesc->sc_rdp = NE2100_RDP;
lesc->sc_card = NE2100;
/*
* Extract the physical MAC address from the ROM.
*/
for (i = 0; i < sizeof(sc->sc_arpcom.ac_enaddr); i++)
sc->sc_arpcom.ac_enaddr[i] = bus_space_read_1(iot, ioh, i);
sc->sc_mem = malloc(16384, M_DEVBUF, M_NOWAIT);
if (sc->sc_mem == 0) {
printf(": couldn't allocate memory for card\n");
return;
}
sc->sc_conf3 = 0;
sc->sc_addr = kvtop(sc->sc_mem);
sc->sc_memsize = 16384;
sc->sc_copytodesc = am7990_copytobuf_contig;
sc->sc_copyfromdesc = am7990_copyfrombuf_contig;
sc->sc_copytobuf = am7990_copytobuf_contig;
sc->sc_copyfrombuf = am7990_copyfrombuf_contig;
sc->sc_zerobuf = am7990_zerobuf_contig;
sc->sc_rdcsr = le_isa_rdcsr;
sc->sc_wrcsr = le_isa_wrcsr;
sc->sc_hwreset = NULL;
sc->sc_hwinit = NULL;
am7990_config(sc);
#if NISADMA > 0
if (ia->ia_drq != DRQUNK)
isadma_cascade(ia->ia_drq);
#endif
lesc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE,
IPL_NET, le_isa_intredge, sc, sc->sc_dev.dv_xname);
}
int
spigot_attach(struct isa_device *devp)
{
struct spigot_softc *ss=(struct spigot_softc *)&spigot_softc[devp->id_unit];
kdc_spigot[devp->id_unit].kdc_state = DC_UNKNOWN;
ss->maddr = kvtop(devp->id_maddr);
ss->irq = devp->id_irq;
return 1;
}
/*
* Loader main routine
*
* We assume that the following machine state has
* been already set before this routine.
* - CPU is initialized.
* - DRAM is configured.
* - Loader BSS section is filled with 0.
* - Loader stack is configured.
* - All interrupts are disabled.
*/
int
main(void)
{
entry_t entry;
memset(bootinfo, 0, BOOTINFOSZ);
/*
* Initialize debug port.
*/
debug_init();
DPRINTF(("Prex Boot Loader\n"));
/*
* Do platform dependent initialization.
*/
startup();
/*
* Show splash screen.
*/
splash();
/*
* Load OS modules to appropriate locations.
*/
load_os();
/*
* Dump boot infomation for debug.
*/
dump_bootinfo();
/*
* Launch kernel.
*/
entry = (entry_t)kvtop(bootinfo->kernel.entry);
DPRINTF(("Entering kernel (at 0x%lx) ...\n\n", (long)entry));
(*entry)();
panic("Oops!");
/* NOTREACHED */
return 0;
}
void
cpu_swapin(struct lwp *l)
{
struct trapframe *tf = l->l_md.md_regs;
/*
* Stash the physical for the pcb of U for later perusal
*/
l->l_addr->u_pcb.pcb_uva = (vaddr_t)l->l_addr;
tf->tf_cr30 = kvtop((caddr_t)l->l_addr);
fdcache(HPPA_SID_KERNEL, (vaddr_t)l->l_addr, sizeof(l->l_addr->u_pcb));
#ifdef HPPA_REDZONE
/* Create the kernel stack red zone. */
pmap_redzone((vaddr_t)l->l_addr + HPPA_REDZONE,
(vaddr_t)l->l_addr + USPACE, 1);
#endif
}
/*
* Machine-dependent startup code
*/
void
machine_startup(void)
{
void *vector_offset = 0;
/*
* Reserve system pages.
*/
page_reserve(kvtop(SYSPAGE), SYSPAGESZ);
/*
* Copy exception vectors.
*/
memcpy(vector_offset, &exception_vector, 0x3000);
#ifdef CONFIG_MMU
/*
* Initialize MMU
*/
mmu_init(mmumap_table);
#endif
}
void
atzscattach(device_t parent, device_t self, void *aux)
{
volatile struct sdmac *rp;
struct sbic_softc *sc = device_private(self);
struct zbus_args *zap;
struct scsipi_adapter *adapt = &sc->sc_adapter;
struct scsipi_channel *chan = &sc->sc_channel;
zap = aux;
sc->sc_dev = self;
sc->sc_cregs = rp = zap->va;
/*
* disable ints and reset bank register
*/
rp->CNTR = CNTR_PDMD;
amiga_membarrier();
rp->DAWR = DAWR_ATZSC;
amiga_membarrier();
sc->sc_enintr = atzsc_enintr;
sc->sc_dmago = atzsc_dmago;
sc->sc_dmanext = atzsc_dmanext;
sc->sc_dmastop = atzsc_dmastop;
sc->sc_dmacmd = 0;
/*
* only 24 bit mem.
*/
sc->sc_flags |= SBICF_BADDMA;
sc->sc_dmamask = ~0x00ffffff;
#if 0
/*
* If the users kva space is not ztwo try and allocate a bounce buffer.
* XXX this needs to change if we move to multiple memory segments.
*/
if (kvtop(sc) & sc->sc_dmamask) {
sc->sc_dmabuffer = (char *)alloc_z2mem(MAXPHYS * 8); /* XXX */
if (isztwomem(sc->sc_dmabuffer))
printf(" bounce pa 0x%x", kvtop(sc->sc_dmabuffer));
else if (sc->sc_dmabuffer)
printf(" bounce pa 0x%x",
PREP_DMA_MEM(sc->sc_dmabuffer));
}
#endif
sc->sc_sbic.sbic_asr_p = (volatile unsigned char *)rp + 0x91;
sc->sc_sbic.sbic_value_p = (volatile unsigned char *)rp + 0x93;
sc->sc_clkfreq = sbic_clock_override ? sbic_clock_override : 77;
printf(": dmamask 0x%lx\n", ~sc->sc_dmamask);
/*
* Fill in the scsipi_adapter.
*/
memset(adapt, 0, sizeof(*adapt));
adapt->adapt_dev = self;
adapt->adapt_nchannels = 1;
adapt->adapt_openings = 7;
adapt->adapt_max_periph = 1;
adapt->adapt_request = sbic_scsipi_request;
adapt->adapt_minphys = sbic_minphys;
/*
* Fill in the scsipi_channel.
*/
memset(chan, 0, sizeof(*chan));
chan->chan_adapter = adapt;
chan->chan_bustype = &scsi_bustype;
chan->chan_channel = 0;
chan->chan_ntargets = 8;
chan->chan_nluns = 8;
chan->chan_id = 7;
sbicinit(sc);
sc->sc_isr.isr_intr = atzsc_dmaintr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 2;
add_isr (&sc->sc_isr);
/*
* attach all scsi units on us
*/
config_found(self, chan, scsiprint);
}
/*---------------------------------------------------------------------------*
* isic_probe_s016 - probe for Teles S0/16 and compatibles
*---------------------------------------------------------------------------*/
int
isic_probe_s016(device_t dev)
{
size_t unit = device_get_unit(dev); /* get unit */
struct l1_softc *sc = 0; /* softc */
void *ih = 0; /* dummy */
u_int8_t b0,b1,b2; /* for signature */
bus_space_tag_t t; /* bus things */
bus_space_handle_t h;
/* check max unit range */
if(unit >= ISIC_MAXUNIT)
{
printf("isic%d: Error, unit %d >= ISIC_MAXUNIT for Teles S0/16!\n",
unit, unit);
return(ENXIO);
}
sc = &l1_sc[unit]; /* get pointer to softc */
sc->sc_unit = unit; /* set unit */
/* see if an io base was supplied */
if(!(sc->sc_resources.io_base[0] =
bus_alloc_resource(dev, SYS_RES_IOPORT,
&sc->sc_resources.io_rid[0],
0ul, ~0ul, 1, RF_ACTIVE)))
{
printf("isic%d: Could not allocate i/o port for Teles S0/16.\n", unit);
return(ENXIO);
}
sc->sc_port = rman_get_start(sc->sc_resources.io_base[0]);
/*
* check if the provided io port is valid
*/
switch(sc->sc_port)
{
case 0xd80:
case 0xe80:
case 0xf80:
break;
default:
printf("isic%d: Error, invalid iobase 0x%x specified for Teles S0/16!\n",
unit, sc->sc_port);
isic_detach_common(dev);
return(ENXIO);
break;
}
/* allocate memory resource */
if(!(sc->sc_resources.mem =
bus_alloc_resource(dev, SYS_RES_MEMORY,
&sc->sc_resources.mem_rid,
0ul, ~0ul, TELES_S016_MEMSIZE,
RF_ACTIVE)))
{
printf("isic%d: Could not allocate memory for Teles S0/16.\n", unit);
isic_detach_common(dev);
return(ENXIO);
}
/*
* get virtual addr.
*/
sc->sc_vmem_addr = rman_get_virtual(sc->sc_resources.mem);
/*
* check for valid adresses
*/
switch(kvtop(sc->sc_vmem_addr))
{
case 0xc0000:
case 0xc2000:
case 0xc4000:
case 0xc6000:
case 0xc8000:
case 0xca000:
case 0xcc000:
case 0xce000:
case 0xd0000:
case 0xd2000:
case 0xd4000:
case 0xd6000:
case 0xd8000:
case 0xda000:
case 0xdc000:
case 0xde000:
break;
default:
printf("isic%d: Error, invalid memory address 0x%lx for Teles S0/16!\n",
unit, kvtop(sc->sc_vmem_addr));
isic_detach_common(dev);
return(ENXIO);
break;
}
/* setup ISAC access routines */
sc->clearirq = NULL;
sc->readreg = tels016_read_reg;
sc->writereg = tels016_write_reg;
sc->readfifo = tels016_read_fifo;
sc->writefifo = tels016_write_fifo;
/* setup card type */
sc->sc_cardtyp = CARD_TYPEP_16;
/* setup IOM bus type */
sc->sc_bustyp = BUS_TYPE_IOM1;
sc->sc_ipac = 0;
sc->sc_bfifolen = HSCX_FIFO_LEN;
/* setup ISAC base addr, though we don't really need it */
ISAC_BASE = (caddr_t)((sc->sc_vmem_addr) + 0x100);
/* setup HSCX base addr */
HSCX_A_BASE = (caddr_t)((sc->sc_vmem_addr) + 0x180);
HSCX_B_BASE = (caddr_t)((sc->sc_vmem_addr) + 0x1c0);
t = rman_get_bustag(sc->sc_resources.io_base[0]);
h = rman_get_bushandle(sc->sc_resources.io_base[0]);
/* get signature bytes */
b0 = bus_space_read_1(t, h, 0);
b1 = bus_space_read_1(t, h, 1);
b2 = bus_space_read_1(t, h, 2);
/* check signature bytes */
if(b0 != 0x51)
{
printf("isic%d: Error, signature 1 0x%x != 0x51 for Teles S0/16!\n",
unit, b0);
isic_detach_common(dev);
return(ENXIO);
}
if(b1 != 0x93)
{
printf("isic%d: Error, signature 2 0x%x != 0x93 for Teles S0/16!\n",
unit, b1);
isic_detach_common(dev);
return(ENXIO);
}
if((b2 != 0x1e) && (b2 != 0x1f))
{
printf("isic%d: Error, signature 3 0x%x != 0x1e or 0x1f for Teles S0/16!\n",
unit, b2);
isic_detach_common(dev);
return(ENXIO);
}
/* get our irq */
if(!(sc->sc_resources.irq =
bus_alloc_resource(dev, SYS_RES_IRQ,
&sc->sc_resources.irq_rid,
0ul, ~0ul, 1, RF_ACTIVE)))
{
printf("isic%d: Could not allocate irq for Teles S0/16.\n", unit);
isic_detach_common(dev);
return ENXIO;
}
/* register interupt routine */
bus_setup_intr(dev, sc->sc_resources.irq,
INTR_TYPE_NET,
(void(*)(void *))(isicintr),
sc, &ih);
/* get the irq number */
sc->sc_irq = rman_get_start(sc->sc_resources.irq);
/* check IRQ validity */
if((intr_no[sc->sc_irq]) == 1)
{
printf("isic%d: Error, invalid IRQ [%d] specified for Teles S0/16!\n",
unit, sc->sc_irq);
isic_detach_common(dev);
return(ENXIO);
}
return (0);
}
hide void
mc_attach(device_t parent, device_t self, void *aux)
{
struct confargs *ca = aux;
struct mc_softc *sc = device_private(self);
u_int8_t myaddr[ETHER_ADDR_LEN];
u_int *reg;
sc->sc_dev = self;
sc->sc_node = ca->ca_node;
sc->sc_regt = ca->ca_tag;
reg = ca->ca_reg;
reg[0] += ca->ca_baseaddr;
reg[2] += ca->ca_baseaddr;
reg[4] += ca->ca_baseaddr;
sc->sc_txdma = mapiodev(reg[2], reg[3], false);
sc->sc_rxdma = mapiodev(reg[4], reg[5], false);
bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh);
sc->sc_tail = 0;
sc->sc_txdmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 2, NULL);
sc->sc_rxdmacmd = (void *)dbdma_alloc(sizeof(dbdma_command_t) * 8,
NULL);
memset(sc->sc_txdmacmd, 0, sizeof(dbdma_command_t) * 2);
memset(sc->sc_rxdmacmd, 0, sizeof(dbdma_command_t) * 8);
printf(": irq %d,%d,%d",
ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]);
if (OF_getprop(sc->sc_node, "local-mac-address", myaddr, 6) != 6) {
printf(": failed to get MAC address.\n");
return;
}
/* allocate memory for transmit buffer and mark it non-cacheable */
sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK);
sc->sc_txbuf_phys = kvtop(sc->sc_txbuf);
memset(sc->sc_txbuf, 0, PAGE_SIZE);
/*
* allocate memory for receive buffer and mark it non-cacheable
* XXX This should use the bus_dma interface, since the buffer
* needs to be physically contiguous. However, it seems that
* at least on my system, malloc() does allocate contiguous
* memory. If it's not, suggest reducing the number of buffers
* to 2, which will fit in one 4K page.
*/
sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK);
sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf);
memset(sc->sc_rxbuf, 0, MC_NPAGES * PAGE_SIZE);
if ((int)sc->sc_txbuf & PGOFSET)
printf("txbuf is not page-aligned\n");
if ((int)sc->sc_rxbuf & PGOFSET)
printf("rxbuf is not page-aligned\n");
sc->sc_bus_init = mc_init;
sc->sc_putpacket = mc_putpacket;
/* disable receive DMA */
dbdma_reset(sc->sc_rxdma);
/* disable transmit DMA */
dbdma_reset(sc->sc_txdma);
/* install interrupt handlers */
/*intr_establish(ca->ca_intr[1], IST_EDGE, IPL_NET, mc_dmaintr, sc);*/
intr_establish(ca->ca_intr[2], IST_EDGE, IPL_NET, mc_dmaintr, sc);
intr_establish(ca->ca_intr[0], IST_EDGE, IPL_NET, mcintr, sc);
sc->sc_biucc = XMTSP_64;
sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU |
XMTBRST | RCVBRST;
/*sc->sc_plscc = PORTSEL_10BT;*/
sc->sc_plscc = PORTSEL_GPSI | ENPLSIO;
/* mcsetup returns 1 if something fails */
if (mcsetup(sc, myaddr)) {
printf("mcsetup returns non zero\n");
return;
}
#ifdef NOTYET
sc->sc_mediachange = mc_mediachange;
sc->sc_mediastatus = mc_mediastatus;
sc->sc_supmedia = mc_supmedia;
sc->sc_nsupmedia = N_SUPMEDIA;
sc->sc_defaultmedia = IFM_ETHER | IFM_10_T;
#endif
}
int
esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
int datain, size_t *dmasize)
{
struct esp_softc *esc = (struct esp_softc *)sc;
dbdma_command_t *cmdp;
u_int cmd;
u_int va;
int count, offset;
cmdp = esc->sc_dmacmd;
cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE;
count = *dmasize;
if (count / PAGE_SIZE > 32)
panic("%s: transfer size >= 128k", device_xname(sc->sc_dev));
esc->sc_dmaaddr = addr;
esc->sc_dmalen = len;
esc->sc_dmasize = count;
va = (u_int)*esc->sc_dmaaddr;
offset = va & PGOFSET;
/* if va is not page-aligned, setup the first page */
if (offset != 0) {
int rest = PAGE_SIZE - offset; /* the rest of the page */
if (count > rest) { /* if continues to next page */
DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((void *)va),
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER,
DBDMA_BRANCH_NEVER);
count -= rest;
va += rest;
cmdp++;
}
}
/* now va is page-aligned */
while (count > PAGE_SIZE) {
DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, kvtop((void *)va),
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
count -= PAGE_SIZE;
va += PAGE_SIZE;
cmdp++;
}
/* the last page (count <= PAGE_SIZE here) */
cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST;
DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((void *)va),
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
cmdp++;
DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0,
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
esc->sc_dma_direction = datain ? D_WRITE : 0;
return 0;
}
static void
empb_callback(device_t self) {
struct empb_softc *sc;
pci_chipset_tag_t pc;
struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif /* PCI_NETBSD_CONFIGURE */
sc = device_private(self);
pc = &sc->apc;
#ifdef EMPB_DEBUG
aprint_normal("empb: mapped setup %x->%x, conf/io %x->%x\n",
kvtop((void*) sc->setup_area.base), sc->setup_area.base,
kvtop((void*) sc->pci_confio_area.base), sc->pci_confio_area.base);
#endif
sc->pci_confio_t = &(sc->pci_confio_area);
/*
* We should not map I/O space here, however we have no choice
* since these addresses are shared between configuration space and
* I/O space. Not really a problem on m68k, however on PPC...
*/
if (bus_space_map(sc->pci_confio_t, 0, EMPB_BRIDGE_SIZE, 0,
&sc->pci_confio_h))
aprint_error_dev(self,
"couldn't map PCI configuration & I/O space\n");
sc->apc.pci_conf_datat = sc->pci_confio_t;
sc->apc.pci_conf_datah = sc->pci_confio_h;
sc->setup_area_t = &(sc->setup_area);
if (bus_space_map(sc->setup_area_t, 0, EMPB_SETUP_SIZE, 0,
&sc->setup_area_h))
aprint_error_dev(self,
"couldn't map Mediator setup space\n");
empb_find_mem(sc);
if (sc->pci_mem_win_size == 0)
aprint_error_dev(self,
"couldn't find memory space, check your WINDOW jumper\n");
/* Initialize the PCI chipset tag. */
sc->apc.pc_conf_v = (void*) pc;
sc->apc.pc_bus_maxdevs = empb_pci_bus_maxdevs;
sc->apc.pc_make_tag = amiga_pci_make_tag;
sc->apc.pc_decompose_tag = amiga_pci_decompose_tag;
sc->apc.pc_conf_read = empb_pci_conf_read;
sc->apc.pc_conf_write = empb_pci_conf_write;
sc->apc.pc_attach_hook = empb_pci_attach_hook;
sc->apc.pc_intr_map = empb_pci_intr_map;
sc->apc.pc_intr_string = amiga_pci_intr_string;
sc->apc.pc_intr_establish = amiga_pci_intr_establish;
sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish;
sc->apc.pc_conf_hook = empb_pci_conf_hook;
sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt;
sc->apc.cookie = sc;
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("empbio", 0, EMPB_BRIDGE_SIZE,
NULL, 0, EX_NOWAIT);
memext = extent_create("empbmem", EMPB_MEM_BASE, EMPB_MEM_END,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
pba.pba_iot = &(sc->pci_confio_area);
pba.pba_dmat = NULL;
pba.pba_dmat64 = NULL;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_IO_OKAY;
if(sc->pci_mem_win_size > 0) {
pba.pba_memt = &(sc->pci_mem_win);
pba.pba_flags |= PCI_FLAGS_MEM_OKAY;
} else
pba.pba_memt = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
/* Attach power management on SX and TX models. */
switch (sc->model) {
case ZORRO_PRODID_MED1K2SX:
case ZORRO_PRODID_MED1K2TX:
empb_empm_attach(sc);
default:
break;
}
empb_intr_enable(sc);
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
static int
load_relocatable(char *img, struct module *m)
{
Elf32_Ehdr *ehdr;
Elf32_Shdr *shdr;
paddr_t sect_base, bss_base;
int i;
strshndx = 0;
ehdr = (Elf32_Ehdr *)img;
shdr = (Elf32_Shdr *)((paddr_t)ehdr + ehdr->e_shoff);
bss_base = 0;
m->phys = load_base;
ELFDBG(("phys addr=%lx\n", load_base));
/* Copy sections */
for (i = 0; i < (int)ehdr->e_shnum; i++, shdr++) {
sect_addr[i] = 0;
if (shdr->sh_type == SHT_PROGBITS) {
ELFDBG(("sh_addr=%x\n", shdr->sh_addr));
ELFDBG(("sh_size=%x\n", shdr->sh_size));
ELFDBG(("sh_offset=%x\n", shdr->sh_offset));
ELFDBG(("sh_flags=%x\n", shdr->sh_flags));
switch (shdr->sh_flags & SHF_VALID) {
case (SHF_ALLOC | SHF_EXECINSTR):
/* Text */
m->text = (vaddr_t)ptokv(load_base);
break;
case (SHF_ALLOC | SHF_WRITE):
/* Data */
if (m->data == 0) {
m->data = (vaddr_t)ptokv(load_base +
shdr->sh_addr);
}
break;
case SHF_ALLOC:
/* rodata */
/* Note: rodata is treated as text. */
break;
default:
continue;
}
sect_base = load_base + shdr->sh_addr;
memcpy((char *)sect_base, img + shdr->sh_offset,
(size_t)shdr->sh_size);
ELFDBG(("load: offset=%lx size=%x\n",
sect_base, (int)shdr->sh_size));
sect_addr[i] = (char *)sect_base;
} else if (shdr->sh_type == SHT_NOBITS) {
/* BSS */
m->bsssz = (size_t)shdr->sh_size;
sect_base = load_base + shdr->sh_addr;
bss_base = sect_base;
/* Zero fill BSS */
memset((char *)bss_base, 0, (size_t)shdr->sh_size);
sect_addr[i] = (char *)sect_base;
} else if (shdr->sh_type == SHT_SYMTAB) {
/* Symbol table */
ELFDBG(("load: symtab index=%d link=%d\n",
i, shdr->sh_link));
sect_addr[i] = img + shdr->sh_offset;
if (strshndx != 0)
panic("Multiple symtab found!");
strshndx = (int)shdr->sh_link;
} else if (shdr->sh_type == SHT_STRTAB) {
/* String table */
sect_addr[i] = img + shdr->sh_offset;
ELFDBG(("load: strtab index=%d addr=%x\n",
i, sect_addr[i]));
}
}
m->textsz = (size_t)(m->data - m->text);
m->datasz = (size_t)((char *)ptokv(bss_base) - m->data);
load_base = bss_base + m->bsssz;
load_base = round_page(load_base);
ELFDBG(("module load_base=%lx text=%lx\n", load_base, m->text));
m->size = (size_t)(load_base - kvtop(m->text));
m->entry = (vaddr_t)ptokv(ehdr->e_entry + m->phys);
ELFDBG(("module size=%x entry=%lx\n", m->size, m->entry));
/* Process relocation */
shdr = (Elf32_Shdr *)((paddr_t)ehdr + ehdr->e_shoff);
for (i = 0; i < (int)ehdr->e_shnum; i++, shdr++) {
if (shdr->sh_type == SHT_REL || shdr->sh_type == SHT_RELA) {
if (relocate_section(img, shdr) != 0) {
DPRINTF(("Relocation error: module=%s\n", m->name));
return -1;
}
}
}
return 0;
}
int
isic_probe_s016(struct isa_device *dev)
{
struct isic_softc *sc = &l1_sc[dev->id_unit];
u_char byte;
/* check max unit range */
if(dev->id_unit >= ISIC_MAXUNIT)
{
printf("isic%d: Error, unit %d >= ISIC_MAXUNIT for Teles S0/16!\n",
dev->id_unit, dev->id_unit);
return(0);
}
sc->sc_unit = dev->id_unit;
/* check IRQ validity */
if((intr_no[ffs(dev->id_irq) - 1]) == 1)
{
printf("isic%d: Error, invalid IRQ [%d] specified for Teles S0/16!\n",
dev->id_unit, ffs(dev->id_irq)-1);
return(0);
}
sc->sc_irq = dev->id_irq;
/* check if we got an iobase */
switch(dev->id_iobase)
{
case 0xd80:
case 0xe80:
case 0xf80:
break;
default:
printf("isic%d: Error, invalid iobase 0x%x specified for Teles S0/16!\n",
dev->id_unit, dev->id_iobase);
return(0);
break;
}
sc->sc_port = dev->id_iobase;
/* check if valid memory addr */
switch((unsigned int)kvtop(dev->id_maddr))
{
case 0xc0000:
case 0xc2000:
case 0xc4000:
case 0xc6000:
case 0xc8000:
case 0xca000:
case 0xcc000:
case 0xce000:
case 0xd0000:
case 0xd2000:
case 0xd4000:
case 0xd6000:
case 0xd8000:
case 0xda000:
case 0xdc000:
case 0xde000:
break;
default:
printf("isic%d: Error, invalid mem addr 0x%lx for Teles S0/16!\n",
dev->id_unit, kvtop(dev->id_maddr));
return(0);
break;
}
sc->sc_vmem_addr = (void *) dev->id_maddr;
dev->id_msize = 0x1000;
/* check card signature */
if((byte = inb(sc->sc_port)) != 0x51)
{
printf("isic%d: Error, signature 1 0x%x != 0x51 for Teles S0/16!\n",
dev->id_unit, byte);
return(0);
}
if((byte = inb(sc->sc_port + 1)) != 0x93)
{
printf("isic%d: Error, signature 2 0x%x != 0x93 for Teles S0/16!\n",
dev->id_unit, byte);
return(0);
}
byte = inb(sc->sc_port + 2);
if((byte != 0x1e) && (byte != 0x1f))
{
printf("isic%d: Error, signature 3 0x%x != 0x1e or 0x1f for Teles S0/16!\n",
dev->id_unit, byte);
return(0);
}
/* setup access routines */
sc->clearirq = NULL;
sc->readreg = tels016_read_reg;
sc->writereg = tels016_write_reg;
sc->readfifo = tels016_memcpyb;
sc->writefifo = tels016_memcpyb;
/* setup card type */
sc->sc_cardtyp= CARD_TYPEP_16;
/* setup IOM bus type */
sc->sc_bustyp = BUS_TYPE_IOM1;
sc->sc_ipac = 0;
sc->sc_bfifolen = HSCX_FIFO_LEN;
/* setup ISAC base addr */
ISAC_BASE = (void *) ((dev->id_maddr) + 0x100);
/* setup HSCX base addr */
HSCX_A_BASE = (void *) ((dev->id_maddr) + 0x180);
HSCX_B_BASE = (void *) ((dev->id_maddr) + 0x1c0);
return (1);
}
static void
mppb_attach(device_t parent, device_t self, void *aux)
{
struct mppb_softc *sc;
struct pcibus_attach_args pba;
struct zbus_args *zap;
pci_chipset_tag_t pc;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif /* PCI_NETBSD_CONFIGURE */
zap = aux;
sc = device_private(self);
pc = &sc->apc;
sc->sc_dev = self;
sc->ba = zap->va;
aprint_normal(": Matay Prometheus PCI bridge\n");
/* Setup bus space mappings. */
sc->pci_conf_area.base = (bus_addr_t) sc->ba + MPPB_CONF_BASE;
sc->pci_conf_area.absm = &amiga_bus_stride_1swap;
sc->pci_mem_area.base = (bus_addr_t) sc->ba + MPPB_MEM_BASE;
sc->pci_mem_area.absm = &amiga_bus_stride_1;
sc->pci_io_area.base = (bus_addr_t) sc->ba + MPPB_IO_BASE;
sc->pci_io_area.absm = &amiga_bus_stride_1;
#ifdef MPPB_DEBUG
aprint_normal("mppb mapped conf %x->%x, mem %x->%x\n, io %x->%x\n",
kvtop((void*) sc->pci_conf_area.base), sc->pci_conf_area.base,
kvtop((void*) sc->pci_mem_area.base), sc->pci_mem_area.base,
kvtop((void*) sc->pci_io_area.base), sc->pci_io_area.base);
#endif
sc->apc.pci_conf_datat = &(sc->pci_conf_area);
if (bus_space_map(sc->apc.pci_conf_datat, 0, MPPB_CONF_SIZE, 0,
&sc->apc.pci_conf_datah))
aprint_error_dev(self,
"couldn't map PCI configuration data space\n");
/* Initialize the PCI chipset tag. */
sc->apc.pc_conf_v = (void*) pc;
sc->apc.pc_bus_maxdevs = mppb_pci_bus_maxdevs;
sc->apc.pc_make_tag = amiga_pci_make_tag;
sc->apc.pc_decompose_tag = amiga_pci_decompose_tag;
sc->apc.pc_conf_read = mppb_pci_conf_read;
sc->apc.pc_conf_write = mppb_pci_conf_write;
sc->apc.pc_attach_hook = mppb_pci_attach_hook;
sc->apc.pc_intr_map = mppb_pci_intr_map;
sc->apc.pc_intr_string = amiga_pci_intr_string;
sc->apc.pc_intr_establish = amiga_pci_intr_establish;
sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish;
sc->apc.pc_conf_hook = amiga_pci_conf_hook;
sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt;
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("mppbio", MPPB_IO_BASE,
MPPB_IO_BASE + MPPB_IO_SIZE, NULL, 0, EX_NOWAIT);
memext = extent_create("mppbmem", MPPB_MEM_BASE,
MPPB_MEM_BASE + MPPB_MEM_SIZE, NULL, 0, EX_NOWAIT);
#ifdef MPPB_DEBUG
aprint_normal("mppb: reconfiguring the bus!\n");
#endif /* MPPB_DEBUG */
pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
pba.pba_iot = &(sc->pci_io_area);
pba.pba_memt = &(sc->pci_mem_area);
pba.pba_dmat = NULL;
pba.pba_dmat64 = NULL;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
/* ******************************************************************** */
RTIP_BOOLEAN r8139_open(PIFACE pi)
{
PR8139_SOFTC sc;
IOADDRESS io_address;
PFBYTE p;
dword l;
int i;
/* Alloc context block */
/* r8139softc[i] = &_r8139softc[i]; */
if (!r8139softc[pi->minor_number])
{
p = (PFBYTE) dcu_alloc_core(sizeof(*sc)+4);
/* make sure on 4 byte boundary first */
l = (dword) p;
while (l & 0x3ul) {
l++;
p++;
};
r8139softc[pi->minor_number] = (PR8139_SOFTC) p;
}
sc = iface_to_r8139_softc(pi);
if (!sc)
return(FALSE);
tc_memset(sc, 0, sizeof(*sc));
#if (INCLUDE_XMIT_QUE)
sc->first_tx = -1;
#endif
#if (defined (RTKBCPP)) /* for power pack we allocate this */
sc->pr8139rxbuf = (PFBYTE) ks_dpmi_alloc((word)(CFG_R8139_RX_BUFLEN + 16)); /* add 16 for alignment */
if (!sc->pr8139rxbuf)
{
DEBUG_ERROR("r8139 - dpmi alloc failed", NOVAR, 0, 0);
return(FALSE);
}
#else
sc->pr8139rxbuf = (PFBYTE) &r8139rxbuf[0];
#endif
if (!sc->pr8139rxbuf)
{
return(FALSE);
}
sc->iface = pi;
pi->driver_stats.ether_stats = (PETHER_STATS)&(sc->stats);
#if (INCLUDE_XMIT_QUE)
pi->xmit_que_depth = TX_RING_SIZE;
#endif
/* Find an8139 type device indexed by minor number */
sc->device_index = r8139_pci_init(pi, &sc->ia_irq, &sc->ia_iobase);
if (sc->device_index<0)
return(FALSE);
pi->io_address = io_address = sc->ia_iobase;
pi->irq_val = sc->ia_irq;
/* Reset the chip and hook the interrupt service routine while waiting */
ks_disable();
R8139_OUTBYTE(io_address + CR_COMMAND,CR_RESET);
#if (RTIP_VERSION > 24)
ks_hook_interrupt(sc->ia_irq, (PFVOID) pi,
(RTIPINTFN_POINTER)r8139_interrupt,
(RTIPINTFN_POINTER)r8139_pre_interrupt,
pi->minor_number);
#else
ks_hook_interrupt(sc->ia_irq, (RTIPINTFN_POINTER)r8139_interrupt,
pi->minor_number);
#endif
ks_enable();
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--)
if ((R8139_INBYTE(io_address + CR_COMMAND) & CR_RESET) == 0)
i=0;
/* The EEPROM initializes the macaddr,config,msr,phy and tw registers
at reset. Read back the MAC address */
for (i = 0; i < 6; i++)
{
pi->addr.my_hw_addr[i] = 0;
pi->addr.my_hw_addr[i] = R8139_INBYTE(io_address + IDR0 +i);
}
/* Enable Tx/Rx before setting tx/rx configs */
R8139_OUTBYTE(io_address + CR_COMMAND,CR_RXENA|CR_TXENA);
/* Initialise the mode to accept broadcast and unicast only. */
sc->rx_mcast[0] = 0; /* receive multicast filter. 0 accepts none */
sc->rx_mcast[1] = 0;
R8139_OUTDWORD(io_address + MAR0, sc->rx_mcast[0]);
R8139_OUTDWORD(io_address + MAR0 + 4, sc->rx_mcast[1]);
sc->rx_config = (dword)((RX_FIFO_THRESH << 13) |
(CFG_R8139_RX_BUFLEN_IDX << 11) |
(RX_DMA_BURST<<8) |
RX_MODE_BROADCAST |
RX_MODE_MULTICAST |
RX_MODE_UNICAST);
R8139_OUTDWORD(io_address + RCR, sc->rx_config);
sc->tx_flag = (TX_FIFO_THRESH<<11) & 0x003f0000l;
set_up_xmit(sc);
#if(PHY_DEFAULT)
/* We'll accept the default speed/duplex and advertisement values to open.
Pick up current values now for reference. */
sc->mii_cr = R8139_INWORD(io_address + MII_CR);
sc->mii_sr = R8139_INWORD(io_address + MII_SR);
sc->mii_anad = R8139_INWORD(io_address + MII_ANAD);
#else
/* We'll force the device into some configuration depending on the definition
of PHY_SETTINGS */
sc->mii_cr = PHY_SETTINGS;
R8139_OUTWORD(io_address + MII_CR,sc->mii_cr);
sc->mii_sr = R8139_INWORD(io_address + MII_SR);
sc->mii_anad = R8139_INWORD(io_address + MII_ANAD);
#endif
/* Point to the receive buffer. Make sure on 4 byte boundary first.
Buffer is allocated in rtipdata.c */
p = (PFBYTE) sc->pr8139rxbuf;
l = (dword) p;
while (l & 0x3ul)
{
l++;
p++;
};
sc->rx_buf = (PFBYTE) p;
R8139_OUTDWORD(io_address + RBSTART,kvtop(p));
R8139_OUTDWORD(io_address + RXMISS,0l); /*clear missed packet counter */
/* Enable all known interrupts by setting the interrupt mask. */
R8139_OUTWORD(io_address + IMR,INT_ALL);
/* Set up a timer to run every three seconds */
sc->cur_ticks = sc->last_rx_ticks = 0; /* watchdog for hung receiver */
return(TRUE);
}
/* ******************************************************************** */
RTIP_BOOLEAN r8139_xmit_done(PIFACE pi, DCU msg, RTIP_BOOLEAN success)
{
PR8139_SOFTC sc;
IOADDRESS io_address;
#if (DEBUG_R8139_XMIT_QUE)
DEBUG_ERROR("rs189_xmit_done: ", DINT2, msg, 0);
#endif
sc = iface_to_r8139_softc(pi);
if (!sc)
return(FALSE);
if (success)
{
/* Update total number of successfully transmitted packets. */
sc->stats.packets_out++;
sc->stats.bytes_out += DCUTOPACKET(msg)->length;
}
else
{
PFBYTE p;
dword l;
int i;
/* We're in serious troble here. Reset and reinitialize the chip */
/* error - record statistics */
sc->stats.errors_out++;
sc->stats.tx_other_errors++;
io_address = sc->ia_iobase;
ks_disable();
R8139_OUTBYTE(io_address + CR_COMMAND,CR_RESET);
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--)
if ((R8139_INBYTE(io_address + CR_COMMAND) & CR_RESET) == 0)
i=0;
/* Enable Tx/Rx before setting tx/rx configs */
#if (INCLUDE_XMIT_QUE)
R8139_OUTBYTE(io_address + CR_COMMAND,CR_RXENA);
#else
R8139_OUTBYTE(io_address + CR_COMMAND,CR_RXENA|CR_TXENA);
#endif
R8139_OUTDWORD(io_address + MAR0, sc->rx_mcast[0]);
R8139_OUTDWORD(io_address + MAR0 + 4, sc->rx_mcast[1]);
R8139_OUTDWORD(io_address + RCR,sc->rx_config);
R8139_OUTDWORD(io_address + TCR,(TX_DMA_BURST<<8)|0x03000000ul);
sc->rx_index = 0;
/* We'll accept the default speed/duplex and advertisement values to re-open.
Pickurrent values now for reference. */
sc->mii_cr = R8139_INWORD(io_address + MII_CR);
sc->mii_sr = R8139_INWORD(io_address + MII_SR);
sc->mii_anad = R8139_INWORD(io_address + MII_ANAD);
/* Point to the receive buffer. Make sure on 4 byte boundary first. Buffer is
allocated in rtipdata.c */
p = (PFBYTE) sc->pr8139rxbuf;
l = (dword) p;
while (l & 0x3ul)
{
l++;
p++;
};
sc->rx_buf = (PFBYTE) p;
R8139_OUTDWORD(io_address + RBSTART,kvtop(p));
R8139_OUTDWORD(io_address + RXMISS,0l);
/*set_rx_mode(dev); may need this */
/*outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); was already done unless reset by rx_mode */
/* Enable all known interrupts by setting the interrupt mask. */
R8139_OUTWORD(io_address + IMR,INT_ALL);
ks_enable();
}
return(TRUE);
}
/* Transmit Routine. The 8139 device requires that the packet data is 32 bit aligned.
It is assumed here that the DCU's were aligned, no checking will be done here. */
int r8139_xmit(PIFACE pi, DCU msg) /*__fn__*/
{
IOADDRESS io_address;
PR8139_SOFTC sc;
int length;
int this_tx;
#if (INCLUDE_XMIT_QUE)
int nxt_tx;
#endif
dword status;
sc = iface_to_r8139_softc(pi);
if (!sc)
return(ENUMDEVICE);
io_address = sc->ia_iobase;
if (msg)
{
length = DCUTOPACKET(msg)->length;
if (length < ETHER_MIN_LEN)
length = ETHER_MIN_LEN;
if (length > ETHERSIZE)
{
DEBUG_ERROR("xmit - length is too large", NOVAR, 0, 0);
length = ETHERSIZE; /* what a terriable hack! */
}
#if (INCLUDE_XMIT_QUE)
/* if we are starting a new block of transfers save the first one */
/* disable transmitter */
if (sc->first_tx == -1)
{
#if (DISABLE_TX)
R8139_OUTBYTE(io_address + CR_COMMAND,CR_RXENA);
#endif
sc->first_tx = this_tx;
}
sc->num_tx++;
#endif
/* get current discriptor and update descriptor pointer */
this_tx = sc->this_tx++;
this_tx &= TX_RING_MASK; /* Wrap to zero if must */
sc->this_tx &= TX_RING_MASK; /* Wrap to zero if must */
sc->tx_dcus[this_tx] = msg;
/* check that we own the descriptor otherwise return error */
status = R8139_INDWORD(io_address + TXSD0 + (this_tx<<2));
if (!(status & TXSTAT_OWN))
{
DEBUG_ERROR("TX Descriptor not owned ", DINT2 , this_tx, status);
return(EOUTPUTFULL);
}
/* write the packet address to the descriptor */
R8139_OUTDWORD(io_address + TXADD0 +(this_tx<<2),
kvtop((PFBYTE)DCUTODATA(msg)));
/* write the length to the descriptor */
R8139_OUTDWORD(io_address + TXSD0 +(this_tx<<2),
sc->tx_flag | length);
#if (DEBUG_R8139_XMIT_QUE)
DEBUG_ERROR("rs189_xmit: msg, this_tx", DINT2, msg, this_tx);
#endif
/* */
#if (INCLUDE_XMIT_QUE)
/* get next descriptor (already calculated above) */
nxt_tx = sc->this_tx;
+ 1;
/* see if we can fit any more packets in the ring buffer */
status = R8139_INDWORD(io_address + TXSD0 + (nxt_tx<<2));
if ( (status & TXSTAT_OWN) && (sc->num_tx <= TX_RING_SIZE) )
{
#if (DEBUG_R8139_XMIT_QUE)
DEBUG_ERROR("r8139_xmit: we can queue more: nxt_tx", EBS_INT1,
nxt_tx, 0);
#endif
return(REPORT_XMIT_MORE);
}
#if (DEBUG_R8139_XMIT_QUE)
else
{
DEBUG_ERROR("r8139_xmit: we can NOT queue more: nxt_tx", EBS_INT1,
nxt_tx, 0);
}
#endif
#endif /* INCLUDE_XMIT_QUE */
} /* if msg */
/* start xmit */
#if (DEBUG_R8139_XMIT_QUE)
DEBUG_ERROR("r8139_xmit: start xmit", NOVAR, 0, 0);
#endif
#if (INCLUDE_XMIT_QUE)
sc->first_tx = -1;
# if (DISABLE_TX)
/* Enable Tx/Rx before setting tx configs */
R8139_OUTBYTE(io_address + CR_COMMAND,CR_RXENA|CR_TXENA);
set_up_xmit(sc);
# endif
#endif
return(0);
}
