static void h3600_audio_init(void *dummy)
{
unsigned long flags;
/* Setup the uarts */
local_irq_save(flags);
GAFR |= (GPIO_SSP_CLK);
GPDR &= ~(GPIO_SSP_CLK);
Ser4SSCR0 = 0;
Ser4SSCR0 = SSCR0_DataSize(16) + SSCR0_TI + SSCR0_SerClkDiv(8);
Ser4SSCR1 = SSCR1_SClkIactL + SSCR1_SClk1P + SSCR1_ExtClk;
Ser4SSCR0 |= SSCR0_SSE;
/* Enable the audio power */
clr_h3600_egpio(IPAQ_EGPIO_CODEC_NRESET);
set_h3600_egpio(IPAQ_EGPIO_AUDIO_ON);
set_h3600_egpio(IPAQ_EGPIO_QMUTE);
local_irq_restore(flags);
/* external clock configuration */
h3600_set_samplerate(audio_samplerate);
/* Wait for the UDA1341 to wake up */
set_h3600_egpio(IPAQ_EGPIO_CODEC_NRESET);
mdelay(1);
/* make the left and right channels unswapped (flip the WS latch ) */
Ser4SSDR = 0;
/* Initialize the UDA1341 internal state */
l3_open(&uda1341);
clr_h3600_egpio(IPAQ_EGPIO_QMUTE);
}
static void pangolin_audio_init(void *dummy)
{
unsigned long flags;
unsigned int mdrefr;
local_irq_save(flags);
/*
* Setup the SSP uart.
*/
PPAR |= PPAR_SPR;
Ser4SSCR0 = SSCR0_DataSize(16) + SSCR0_TI + SSCR0_SerClkDiv(2);
Ser4SSCR1 = SSCR1_SClkIactL + SSCR1_SClk1P + SSCR1_ExtClk;
GAFR |= GPIO_SSP_TXD | GPIO_SSP_RXD | GPIO_SSP_SCLK | GPIO_SSP_CLK |
GPIO_SSP_SFRM;
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPDR &= ~(GPIO_SSP_RXD | GPIO_SSP_CLK);
Ser4SSCR0 |= SSCR0_SSE;
GAFR &= ~(SpeakerOffPin | QmutePin);
GPDR |= (SpeakerOffPin | QmutePin);
GPCR = SpeakerOffPin;
/*
* The assabet board uses the SDRAM clock as the source clock for
* audio. This is supplied to the SA11x0 from the CPLD on pin 19.
* At 206MHz we need to run the audio clock (SDRAM bank 2)
* at half speed. This clock will scale with core frequency so
* the audio sample rate will also scale. The CPLD on Assabet
* will need to be programmed to match the core frequency.
*/
mdrefr = MDREFR;
if ((mdrefr & (MDREFR_K2DB2 | MDREFR_K2RUN | MDREFR_EAPD |
MDREFR_KAPD)) != (MDREFR_K2DB2 | MDREFR_K2RUN)) {
mdrefr |= MDREFR_K2DB2 | MDREFR_K2RUN;
mdrefr &= ~(MDREFR_EAPD | MDREFR_KAPD);
MDREFR = mdrefr;
(void) MDREFR;
}
local_irq_restore(flags);
/* Wait for the UDA1341 to wake up */
mdelay(100);
l3_open(&uda1341);
pangolin_set_samplerate(audio_samplerate);
GPCR = QmutePin;
}
static void sa1111_audio_init(void *dummy)
{
#ifdef CONFIG_ASSABET_NEPONSET
if (machine_is_assabet()) {
/* Select I2S audio (instead of AC-Link) */
AUD_CTL = AUD_SEL_1341;
}
#endif
#ifdef CONFIG_SA1100_JORNADA720
if (machine_is_jornada720()) {
/* LDD4 is speaker, LDD3 is microphone */
PPSR &= ~(PPC_LDD3 | PPC_LDD4);
PPDR |= PPC_LDD3 | PPC_LDD4;
PPSR |= PPC_LDD4; /* enable speaker */
PPSR |= PPC_LDD3; /* enable microphone */
}
#endif
SBI_SKCR &= ~SKCR_SELAC;
/* Enable the I2S clock and L3 bus clock: */
SKPCR |= (SKPCR_I2SCLKEN | SKPCR_L3CLKEN);
/* Activate and reset the Serial Audio Controller */
SACR0 |= (SACR0_ENB | SACR0_RST);
mdelay(5);
SACR0 &= ~SACR0_RST;
/* For I2S, BIT_CLK is supplied internally. The "SA-1111
* Specification Update" mentions that the BCKD bit should
* be interpreted as "0 = output". Default clock divider
* is 22.05kHz.
*
* Select I2S, L3 bus. "Recording" and "Replaying"
* (receive and transmit) are enabled.
*/
SACR1 = SACR1_L3EN;
SKAUD = audio_clk_div - 1;
/* Initialize the UDA1341 internal state */
l3_open(&uda1341);
}
/*
* Initialise the Assabet audio driver.
*
* Note that we have to be careful with the order that we do things here;
* there is a D-type flip flop which is clocked from the SFRM line which
* indicates whether the same is for the left or right channel to the
* UDA1341.
*
* When you disable the SSP (by clearing SSCR0_SSE) it appears that the
* SFRM signal can float high. When you re-enable the SSP, you clock the
* flip flop once, and end up swapping the left and right channels.
*
* The ASSABET_BCR_CODEC_RST line will force this flip flop into a known
* state, but this line resets other devices as well!
*
* In addition to the above, it appears that powering down the UDA1341 on
* early Assabets leaves the UDA_WS actively driving a logic '1' into the
* chip, wasting power! (you can tell this by D11 being half-on). We
* attempt to correct this by kicking the flip flop on init/open/close.
* We should probably do this on PM resume as well.
*
* (Note the ordering of ASSABET_BCR_AUDIO_ON, SFRM and ASSABET_BCR_CODEC_RST
* is important).
*/
static void assabet_audio_init(void *dummy)
{
unsigned long flags;
unsigned int mdrefr;
local_irq_save(flags);
/*
* Enable the power for the UDA1341 before driving any signals.
* We leave the audio amp (LM4880) disabled for now.
*/
ASSABET_BCR_set(ASSABET_BCR_AUDIO_ON);
#ifdef FIX_POWER_DRAIN
GPSR = GPIO_SSP_SFRM;
GPCR = GPIO_SSP_SFRM;
#endif
ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
ASSABET_BCR_clear(ASSABET_BCR_STEREO_LB);
/*
* Setup the SSP uart.
*/
PPAR |= PPAR_SPR;
Ser4SSCR0 = SSCR0_DataSize(16) + SSCR0_TI + SSCR0_SerClkDiv(2);
Ser4SSCR1 = SSCR1_SClkIactL + SSCR1_SClk1P + SSCR1_ExtClk;
GAFR |= GPIO_SSP_TXD | GPIO_SSP_RXD | GPIO_SSP_SCLK | GPIO_SSP_CLK;
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPDR &= ~(GPIO_SSP_RXD | GPIO_SSP_CLK);
Ser4SSCR0 |= SSCR0_SSE;
/*
* Only give SFRM to the SSP after it has been enabled.
*/
GAFR |= GPIO_SSP_SFRM;
/*
* The assabet board uses the SDRAM clock as the source clock for
* audio. This is supplied to the SA11x0 from the CPLD on pin 19.
* At 206MHz we need to run the audio clock (SDRAM bank 2)
* at half speed. This clock will scale with core frequency so
* the audio sample rate will also scale. The CPLD on Assabet
* will need to be programmed to match the core frequency.
*/
mdrefr = MDREFR;
if ((mdrefr & (MDREFR_K2DB2 | MDREFR_K2RUN | MDREFR_EAPD |
MDREFR_KAPD)) != (MDREFR_K2DB2 | MDREFR_K2RUN)) {
mdrefr |= MDREFR_K2DB2 | MDREFR_K2RUN;
mdrefr &= ~(MDREFR_EAPD | MDREFR_KAPD);
MDREFR = mdrefr;
(void) MDREFR;
}
local_irq_restore(flags);
/* Wait for the UDA1341 to wake up */
mdelay(1);
l3_open(&uda1341);
assabet_set_samplerate(audio_samplerate);
/* Enable the audio power */
ASSABET_BCR_clear(ASSABET_BCR_QMUTE | ASSABET_BCR_SPK_OFF);
}
static void omap1510_audio_init(void *dummy)
{
dma_regs_t *dma_regs = output_stream.dma_regs;
u8 fpga;
printk(__FUNCTION__ "called\n");
/*
Init FPGA.
Turn on Audio amplifier and set 12.288 MHz clock
*/
fpga = fpga_read(OMAP1510P1_FPGA_POWER);
fpga &= 0xfe;
fpga_write(fpga, OMAP1510P1_FPGA_POWER);
fpga = 0xc;
fpga_write(fpga, OMAP1510P1_FPGA_AUDIO);
#ifndef CONFIG_DSP_MCBSP1
/*
Now here's an ugly hack. To use McBSP1, you need to enable
a clock on the DSP. So enable the MPUI, set the clock,
and start the DSP.
An even uglier, evil hack. If this is going to take the DSP
out of reset, shove an idle loop at the reset vector
and make it loop instead of crash. You will still see
a DSP watchdog timer go off.
*/
{
u16 tmp;
u8 c55_start[] = { 0x7A, 0x00, 0x00, 0x0C, 0x4A, 0x7A, 0x20, 0x20, 0x20, 0x20 };
tmp = inw(ARM_RSTCT1);
// check if DSP is up
if (!(tmp & (ARM_RSTCT1_DSP_RST|ARM_RSTCT1_DSP_EN))) {
if (!(tmp & ARM_RSTCT1_DSP_RST)) { // MPUI in reset
tmp |= ARM_RSTCT1_DSP_RST;
outw(tmp, ARM_RSTCT1);
ck_enable(api_ck);
}
// REVISIT: I'm not finding this in the OMAP1509 TRM:
tmp = inw(0xe1008008);
if (0 == (tmp & 0x2)) { // DSP CLKM enable
tmp |= 0x2;
outw(tmp, 0xe1008008);
}
tmp = inw(0xe1008014);
if (0 == (tmp & 0x1)) { // DSP PER_EN bit
tmp |= 0x1;
outw(tmp, 0xe1008014);
}
tmp = inw(ARM_CKCTL); // Enable DSP
tmp |= 0x2000;
outw(tmp, ARM_CKCTL);
// Write C55 code at reset vector.
memcpy((OMAP_DSP_BASE + 0x4c000),
&c55_start,
sizeof(c55_start));
outw(0x5, MPUI_DSP_BOOT_CONFIG); // Set DSP boot mode
tmp = inw(ARM_RSTCT1); // take DSP out of reset
tmp |= ARM_RSTCT1_DSP_RST|ARM_RSTCT1_DSP_EN;
outw(tmp, ARM_RSTCT1);
} else {
// DSP's up, just check the clock/per bits
tmp = inw(0xe1008008);
if (0 == (tmp & 0x2)) { // DSP CLKM enable
tmp |= 0x2;
outw(tmp, 0xe1008008);
}
tmp = inw(0xe1008014);
if (0 == (tmp & 0x1)) { // DSP PER_EN bit
tmp |= 0x1;
outw(tmp, 0xe1008014);
}
}
}
/*
While we're waiting for the UDA1341 to wake up, let's configure the
DMA channel and MCBSP.
*/
// Setup DMA channel to McBSP1 audio Tx.
dma_regs->csdp = 0x0a01;
dma_regs->ccr = 0x1000 | audio_state.output_dma; // source auto increment, don't enable yet
dma_regs->cicr = 0x0b;
dma_regs->cdsa_l = ((OMAP1510_MCBSP1_BASE + 0x806) & 0xffff); //McBSP1 DXR1
dma_regs->cdsa_u = ((OMAP1510_MCBSP1_BASE + 0x806) >> 16);
dma_regs->cfn = 0x1;
omap_dma_setup(audio_state.output_dma, eDmaOut);
// Initialize McBSP channel
outw(0x0000, OMAP1510_MCBSP1_BASE + 0x80a); // SPCR1
outw(0x0000, OMAP1510_MCBSP1_BASE + 0x808); // SPCR2
outw(0x0f03, OMAP1510_MCBSP1_BASE + 0x824); // PCR0
outw(0x0040, OMAP1510_MCBSP1_BASE + 0x80e); // RCR1
outw(0x8045, OMAP1510_MCBSP1_BASE + 0x80c); // RCR2
outw(0x0040, OMAP1510_MCBSP1_BASE + 0x812); // XCR1
outw(0x8041, OMAP1510_MCBSP1_BASE + 0x810); // XCR2
outw(0x0f0b, OMAP1510_MCBSP1_BASE + 0x816); // SRGR1
outw(0x101f, OMAP1510_MCBSP1_BASE + 0x814); // SRGR2
outw(0x0001, OMAP1510_MCBSP1_BASE + 0x80a); // SPCR1 enable
outw(0x03f1, OMAP1510_MCBSP1_BASE + 0x808); // SPCR2 enable
#endif
/* Wait for the UDA1341 to wake up */
mdelay(1);
/* external clock configuration */
omap1510_set_samplerate(audio_samplerate);
/* Initialize the UDA1341 internal state */
l3_open(&uda1341);
}
