void main_ap(void)
{
// Load the IDT
idt_load((uintptr_t) &idt_data, IDT_LENGTH);
// Enable LAPIC and calibrate the timer
lapic_setup();
lapic_timer_calibrate();
// Setup stack mapping
kernel_map_stack();
// Setup fast syscall support
syscall_init();
// Signal complete AP startup
++smp_ready_count;
// Wait for main entry barrier, then enter the kernel (or halt)
while (main_entry_barrier == 1);
kernel_enter_ap();
}
void main_bsp(void)
{
// Print header
screen_write("Hydrogen v0.2b - http://github.com/farok/H2", 0, 0);
screen_write("Copyright (c) 2012 by Lukas Heidemann", 0, 1);
screen_write("-------------------------------------------------", 0, 2);
// Load the IDT
idt_load(idt_address, IDT_LENGTH);
idt_setup_loader();
// Initialize Hydrogen info tables and parse the multiboot tables
info_init();
multiboot_parse();
// Setup the heap
heap_init();
// Now parse the ACPI tables and analyze the IO APICs
acpi_parse();
ioapic_analyze();
// Find, check and load the kernel binary
kernel_find();
kernel_check();
elf64_load(kernel_binary);
kernel_analyze();
// Initialize interrupt controllers
lapic_detect();
lapic_setup();
ioapic_setup_loader();
pic_setup();
// Calibrate the LAPIC timer
lapic_timer_calibrate();
// Boot APs
info_cpu[lapic_id()].flags |= HY_INFO_CPU_FLAG_BSP;
smp_setup();
// Setup IDT and IOAPIC according to kernel header
idt_setup_kernel();
ioapic_setup_kernel();
// Setup fast syscall support
syscall_init();
// Setup mapping
kernel_map_info();
kernel_map_stack();
kernel_map_idt();
kernel_map_gdt();
// Set free address
info_root->free_paddr = (heap_top + 0xFFF) & ~0xFFF;
// Lower main entry barrier and jump to the kernel entry point
main_entry_barrier = 0;
kernel_enter_bsp();
}
/*
* Enable LAPIC, configure interrupts.
*/
void
lapic_init(boolean_t bsp)
{
uint32_t timer;
u_int temp;
/*
* Install vectors
*
* Since IDT is shared between BSP and APs, these vectors
* only need to be installed once; we do it on BSP.
*/
if (bsp) {
if (cpu_vendor_id == CPU_VENDOR_AMD &&
CPUID_TO_FAMILY(cpu_id) >= 0xf) {
uint32_t tcr;
/*
* Set the LINTEN bit in the HyperTransport
* Transaction Control Register.
*
* This will cause EXTINT and NMI interrupts
* routed over the hypertransport bus to be
* fed into the LAPIC LINT0/LINT1. If the bit
* isn't set, the interrupts will go to the
* general cpu INTR/NMI pins. On a dual-core
* cpu the interrupt winds up going to BOTH cpus.
* The first cpu that does the interrupt ack
* cycle will get the correct interrupt. The
* second cpu that does it will get a spurious
* interrupt vector (typically IRQ 7).
*/
outl(0x0cf8,
(1 << 31) | /* enable */
(0 << 16) | /* bus */
(0x18 << 11) | /* dev (cpu + 0x18) */
(0 << 8) | /* func */
0x68 /* reg */
);
tcr = inl(0xcfc);
if ((tcr & 0x00010000) == 0) {
kprintf("LAPIC: AMD LINTEN on\n");
outl(0xcfc, tcr|0x00010000);
}
outl(0x0cf8, 0);
}
/* Install a 'Spurious INTerrupt' vector */
setidt_global(XSPURIOUSINT_OFFSET, Xspuriousint,
SDT_SYSIGT, SEL_KPL, 0);
/* Install a timer vector */
setidt_global(XTIMER_OFFSET, Xtimer,
SDT_SYSIGT, SEL_KPL, 0);
/* Install an inter-CPU IPI for TLB invalidation */
setidt_global(XINVLTLB_OFFSET, Xinvltlb,
SDT_SYSIGT, SEL_KPL, 0);
/* Install an inter-CPU IPI for IPIQ messaging */
setidt_global(XIPIQ_OFFSET, Xipiq,
SDT_SYSIGT, SEL_KPL, 0);
/* Install an inter-CPU IPI for CPU stop/restart */
setidt_global(XCPUSTOP_OFFSET, Xcpustop,
SDT_SYSIGT, SEL_KPL, 0);
}
/*
* Setup LINT0 as ExtINT on the BSP. This is theoretically an
* aggregate interrupt input from the 8259. The INTA cycle
* will be routed to the external controller (the 8259) which
* is expected to supply the vector.
*
* Must be setup edge triggered, active high.
*
* Disable LINT0 on BSP, if I/O APIC is enabled.
*
* Disable LINT0 on the APs. It doesn't matter what delivery
* mode we use because we leave it masked.
*/
temp = lapic->lvt_lint0;
temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
if (bsp) {
temp |= APIC_LVT_DM_EXTINT;
if (ioapic_enable)
temp |= APIC_LVT_MASKED;
} else {
temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
}
lapic->lvt_lint0 = temp;
/*
* Setup LINT1 as NMI.
*
* Must be setup edge trigger, active high.
*
* Enable LINT1 on BSP, if I/O APIC is enabled.
*
* Disable LINT1 on the APs.
*/
temp = lapic->lvt_lint1;
temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
if (bsp && ioapic_enable)
temp &= ~APIC_LVT_MASKED;
lapic->lvt_lint1 = temp;
/*
* Mask the LAPIC error interrupt, LAPIC performance counter
* interrupt.
*/
lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
/*
* Set LAPIC timer vector and mask the LAPIC timer interrupt.
*/
timer = lapic->lvt_timer;
timer &= ~APIC_LVTT_VECTOR;
timer |= XTIMER_OFFSET;
timer |= APIC_LVTT_MASKED;
lapic->lvt_timer = timer;
/*
* Set the Task Priority Register as needed. At the moment allow
* interrupts on all cpus (the APs will remain CLId until they are
* ready to deal).
*/
temp = lapic->tpr;
temp &= ~APIC_TPR_PRIO; /* clear priority field */
lapic->tpr = temp;
/*
* Enable the LAPIC
*/
temp = lapic->svr;
temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
/*
* Set the spurious interrupt vector. The low 4 bits of the vector
* must be 1111.
*/
if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
temp &= ~APIC_SVR_VECTOR;
temp |= XSPURIOUSINT_OFFSET;
lapic->svr = temp;
/*
* Pump out a few EOIs to clean out interrupts that got through
* before we were able to set the TPR.
*/
lapic->eoi = 0;
lapic->eoi = 0;
lapic->eoi = 0;
if (bsp) {
lapic_timer_calibrate();
if (lapic_timer_enable) {
cputimer_intr_register(&lapic_cputimer_intr);
cputimer_intr_select(&lapic_cputimer_intr, 0);
}
} else {
lapic_timer_set_divisor(lapic_timer_divisor_idx);
}
if (bootverbose)
apic_dump("apic_initialize()");
}
