static int load_asic(struct echoaudio *chip)
{
int box_type, err;
if (chip->asic_loaded)
return 0;
/* Give the DSP a few milliseconds to settle down */
mdelay(2);
err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC,
&card_fw[FW_3G_ASIC]);
if (err < 0)
return err;
chip->asic_code = &card_fw[FW_3G_ASIC];
/* Now give the new ASIC some time to set up */
msleep(1000);
/* See if it worked */
box_type = check_asic_status(chip);
/* Set up the control register if the load succeeded -
* 48 kHz, internal clock, S/PDIF RCA mode */
if (box_type >= 0) {
err = write_control_reg(chip, E3G_48KHZ,
E3G_FREQ_REG_DEFAULT, TRUE);
if (err < 0)
return err;
}
return box_type;
}
/* Depending on what digital mode you want, Mona needs different ASICs
loaded. This function checks the ASIC needed for the new mode and sees
if it matches the one already loaded. */
static int switch_asic(struct echoaudio *chip, char double_speed)
{
int err;
short asic;
/* Check the clock detect bits to see if this is
a single-speed clock or a double-speed clock; load
a new ASIC if necessary. */
if (chip->device_id == DEVICE_ID_56361) {
if (double_speed)
asic = FW_MONA_361_1_ASIC96;
else
asic = FW_MONA_361_1_ASIC48;
} else {
if (double_speed)
asic = FW_MONA_301_1_ASIC96;
else
asic = FW_MONA_301_1_ASIC48;
}
if (asic != chip->asic_code) {
/* Load the desired ASIC */
err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
asic);
if (err < 0)
return err;
chip->asic_code = asic;
}
return 0;
}
/* Mona has an ASIC on the PCI card and another ASIC in the external box;
both need to be loaded. */
static int load_asic(struct echoaudio *chip)
{
u32 control_reg;
int err;
short asic;
if (chip->asic_loaded)
return 0;
mdelay(10);
if (chip->device_id == DEVICE_ID_56361)
asic = FW_MONA_361_1_ASIC48;
else
asic = FW_MONA_301_1_ASIC48;
err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic);
if (err < 0)
return err;
chip->asic_code = asic;
mdelay(10);
/* Do the external one */
err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC,
FW_MONA_2_ASIC);
if (err < 0)
return err;
mdelay(10);
err = check_asic_status(chip);
/* Set up the control register if the load succeeded -
48 kHz, internal clock, S/PDIF RCA mode */
if (!err) {
control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
err = write_control_reg(chip, control_reg, true);
}
return err;
}
/* Layla20 has an ASIC in the external box */
static int load_asic(struct echoaudio *chip)
{
int err;
if (chip->asic_loaded)
return 0;
err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA_ASIC,
&card_fw[FW_LAYLA20_ASIC]);
if (err < 0)
return err;
/* Check if ASIC is alive and well. */
return check_asic_status(chip);
}
/* Gina24 has an ASIC on the PCI card which must be loaded for anything
interesting to happen. */
static int load_asic(struct echoaudio *chip)
{
u32 control_reg;
int err;
short asic;
if (chip->asic_loaded)
return 1;
/* Give the DSP a few milliseconds to settle down */
mdelay(10);
/* Pick the correct ASIC for '301 or '361 Gina24 */
if (chip->device_id == DEVICE_ID_56361)
asic = FW_GINA24_361_ASIC;
else
asic = FW_GINA24_301_ASIC;
err = load_asic_generic(chip, DSP_FNC_LOAD_GINA24_ASIC, asic);
if (err < 0)
return err;
chip->asic_code = asic;
/* Now give the new ASIC a little time to set up */
mdelay(10);
/* See if it worked */
err = check_asic_status(chip);
/* Set up the control register if the load succeeded -
48 kHz, internal clock, S/PDIF RCA mode */
if (!err) {
control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
err = write_control_reg(chip, control_reg, TRUE);
}
DE_INIT(("load_asic() done\n"));
return err;
}
static int load_asic(struct echoaudio *chip)
{
u32 control_reg;
int err;
short asic;
if (chip->asic_loaded)
return 1;
mdelay(10);
if (chip->device_id == DEVICE_ID_56361)
asic = FW_GINA24_361_ASIC;
else
asic = FW_GINA24_301_ASIC;
err = load_asic_generic(chip, DSP_FNC_LOAD_GINA24_ASIC, asic);
if (err < 0)
return err;
chip->asic_code = asic;
mdelay(10);
err = check_asic_status(chip);
if (!err) {
control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
err = write_control_reg(chip, control_reg, TRUE);
}
DE_INIT(("load_asic() done\n"));
return err;
}
static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
u32 control_reg, clock;
short asic;
char force_write;
/* Only set the clock for internal mode. */
if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
dev_dbg(chip->card->dev,
"Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
/* Save the rate anyhow */
chip->comm_page->sample_rate = cpu_to_le32(rate);
chip->sample_rate = rate;
return 0;
}
/* Now, check to see if the required ASIC is loaded */
if (rate >= 88200) {
if (chip->digital_mode == DIGITAL_MODE_ADAT)
return -EINVAL;
if (chip->device_id == DEVICE_ID_56361)
asic = FW_MONA_361_1_ASIC96;
else
asic = FW_MONA_301_1_ASIC96;
} else {
if (chip->device_id == DEVICE_ID_56361)
asic = FW_MONA_361_1_ASIC48;
else
asic = FW_MONA_301_1_ASIC48;
}
force_write = 0;
if (asic != chip->asic_code) {
int err;
/* Load the desired ASIC (load_asic_generic() can sleep) */
spin_unlock_irq(&chip->lock);
err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
asic);
spin_lock_irq(&chip->lock);
if (err < 0)
return err;
chip->asic_code = asic;
force_write = 1;
}
/* Compute the new control register value */
clock = 0;
control_reg = le32_to_cpu(chip->comm_page->control_register);
control_reg &= GML_CLOCK_CLEAR_MASK;
control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
switch (rate) {
case 96000:
clock = GML_96KHZ;
break;
case 88200:
clock = GML_88KHZ;
break;
case 48000:
clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
break;
case 44100:
clock = GML_44KHZ;
/* Professional mode */
if (control_reg & GML_SPDIF_PRO_MODE)
clock |= GML_SPDIF_SAMPLE_RATE0;
break;
case 32000:
clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
GML_SPDIF_SAMPLE_RATE1;
break;
case 22050:
clock = GML_22KHZ;
break;
case 16000:
clock = GML_16KHZ;
break;
case 11025:
clock = GML_11KHZ;
break;
case 8000:
clock = GML_8KHZ;
break;
default:
dev_err(chip->card->dev,
"set_sample_rate: %d invalid!\n", rate);
return -EINVAL;
}
control_reg |= clock;
chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
chip->sample_rate = rate;
dev_dbg(chip->card->dev,
"set_sample_rate: %d clock %d\n", rate, clock);
return write_control_reg(chip, control_reg, force_write);
}
