/* The port A alternate register is an alternate register for reading the port A pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
the instantaneous pin level is read and no input latching is performed except at the
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
uint8_t pit68230_device::rr_pitreg_paar()
{
uint8_t ret;
ret = m_pa_in_cb.isnull() ? 0 : m_pa_in_cb();
LOGR("%s %s <- %02x\n",tag(), FUNCNAME, ret);
return ret;
}
/* The port A alternate register is an alternate register for reading the port A pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
the instantaneous pin level is read and no input latching is performed except at the
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
UINT8 pit68230_device::rr_pitreg_paar()
{
// NOTE: no side effect emulated so using ..padr
UINT8 ret;
ret = m_pa_in_cb();
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, ret));
return ret;
}
uint8_t pit68230_device::rr_pitreg_padr()
{
m_padr &= m_paddr;
if (!m_pa_in_cb.isnull())
{
m_padr |= (m_pa_in_cb() & ~m_paddr);
}
else
{
m_padr |= (m_pail & ~m_paddr);
}
LOGDR("%s %s <- %02x\n",tag(), FUNCNAME, m_padr);
return m_padr;
}
