static __init int bast_irq_init(void)
{
unsigned int i;
if (machine_is_bast()) {
printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");
/* zap all the IRQs */
__raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
/* register our IRQs */
for (i = 0; i < 4; i++) {
unsigned int irqno = bast_pc104_irqs[i];
irq_set_chip_and_handler(irqno, &bast_pc104_chip,
handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
return 0;
}
static __init int bast_ide_init(void)
{
if (machine_is_bast() || machine_is_vr1000())
return platform_add_devices(bast_ide_devices,
ARRAY_SIZE(bast_ide_devices));
return 0;
}
static int __init serial_bast_init(void)
{
if (machine_is_bast()) {
port[0] = serial_bast_register(SERIAL_BASE + 0x2f8, IRQ_PCSERIAL1);
port[1] = serial_bast_register(SERIAL_BASE + 0x3f8, IRQ_PCSERIAL2);
}
return 0;
}
static int __init bastide_init(void)
{
/* we can treat the VR1000 and the BAST the same */
if (!(machine_is_bast() || machine_is_vr1000()))
return 0;
printk("BAST: IDE driver, (c) 2003-2004 Simtec Electronics\n");
bastide_register(BAST_VA_IDEPRI, BAST_VA_IDEPRIAUX, IRQ_IDE0, &ifs[0]);
bastide_register(BAST_VA_IDESEC, BAST_VA_IDESECAUX, IRQ_IDE1, &ifs[1]);
return 0;
}
static __init int pm_simtec_init(void)
{
unsigned long gstatus4;
/* check which machine we are running on */
if (!machine_is_bast() && !machine_is_vr1000() && !machine_is_anubis())
return 0;
printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n");
gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK);
__raw_writel(gstatus4, S3C2410_GSTATUS4);
return s3c2410_pm_init();
}
/*
* Set up timer interrupt, and return the current time in seconds.
*
* Currently we only use timer4, as it is the only timer which has no
* other function that can be exploited externally
*/
void __init s3c2410_init_time (void)
{
unsigned long tcon;
unsigned long tcnt;
unsigned long tcfg1;
unsigned long tcfg0;
gettimeoffset = s3c2410_gettimeoffset;
tcnt = 0xffff; /* default value for tcnt */
/* read the current timer configuration bits */
tcon = __raw_readl(S3C2410_TCON);
tcfg1 = __raw_readl(S3C2410_TCFG1);
tcfg0 = __raw_readl(S3C2410_TCFG0);
/* configure the system for whichever machine is in use */
if (machine_is_bast() || machine_is_vr1000()) {
timer_ticks_usec = 12; /* timer is at 12MHz */
tcnt = (timer_ticks_usec * (1000*1000)) / HZ;
}
/* for the h1940, we use the pclk from the core to generate
* the timer values. since 67.5MHz is not a value we can directly
* generate the timer value from, we need to pre-scale and
* divied before using it.
*
* overall divsior to get 200Hz is 337500
* we can fit tcnt if we pre-scale by 6, producing a tick rate
* of 11.25MHz, and a tcnt of 56250.
*/
if (machine_is_h1940() || machine_is_smdk2410() ) {
timer_ticks_usec = s3c2410_pclk / (1000*1000);
timer_ticks_usec /= 6;
tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
tcnt = (s3c2410_pclk / 6) / HZ;
}
printk("setup_timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx\n",
tcon, tcnt, tcfg0, tcfg1);
/* check to see if timer is within 16bit range... */
if (tcnt > 0xffff) {
panic("setup_timer: HZ is too small, cannot configure timer!");
return;
}
__raw_writel(tcfg1, S3C2410_TCFG1);
__raw_writel(tcfg0, S3C2410_TCFG0);
timer_startval = tcnt;
__raw_writel(tcnt, S3C2410_TCNTB(4));
/* ensure timer is stopped... */
tcon &= ~(7<<20);
tcon |= S3C2410_TCON_T4RELOAD;
tcon |= S3C2410_TCON_T4MANUALUPD;
__raw_writel(tcon, S3C2410_TCON);
__raw_writel(tcnt, S3C2410_TCNTB(4));
__raw_writel(tcnt, S3C2410_TCMPB(4));
setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
/* start the timer running */
tcon |= S3C2410_TCON_T4START;
tcon &= ~S3C2410_TCON_T4MANUALUPD;
__raw_writel(tcon, S3C2410_TCON);
}
