Exemplo n.º 1
0
bool antenna_changed(struct setting *s, const char *val)
{
  if (s->type->from_string(s->type->priv, s->addr, s->len, val))
  {
    max2769_conf1 &= MAX2769_CONF1_LNAMODE_MASK;

    switch (antenna) {
    default:
    case AUTO:
      max2769_conf1 |= MAX2769_CONF1_LNAMODE_GATED;
      break;
    case PATCH:
      max2769_conf1 |= MAX2769_CONF1_LNAMODE_LNA1;
      break;
    case EXTERNAL:
      max2769_conf1 |= MAX2769_CONF1_LNAMODE_LNA2;
      break;
    }
    max2769_write(MAX2769_CONF1, max2769_conf1);
    printf("Antenna changed to: %s\n", val);

    return true;
  }
  return false;
}
Exemplo n.º 2
0
/** Setup MAX2769 GPIOs and write default settings to MAX2769 registers. */
void max2769_setup(void)
{
  /* Setup MAX2769 PGM (PB8) - low */
  RCC_AHB1ENR |= RCC_AHB1ENR_IOPBEN;
  gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, GPIO8);
  gpio_clear(GPIOB, GPIO8);

  /* Setup MAX2769 NSHDN (PB9) - high */
  gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO9);
  gpio_set(GPIOB, GPIO9);

  /* Setup MAX2769 NIDLE (PB10) - high */
  gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO10);
  gpio_set(GPIOB, GPIO10);

  max2769_write(MAX2769_CONF1, MAX2769_CONF1_CHIPEN |
                MAX2769_CONF1_ILNA1(15) |
                MAX2769_CONF1_ILNA2(3) |
                MAX2769_CONF1_ILO(3) |
                MAX2769_CONF1_IMIX(3) |
                MAX2769_CONF1_MIXPOLE_13MHZ |
                MAX2769_CONF1_MIXEN |
                MAX2769_CONF1_ANTEN |
                //MAX2769_CONF1_FCEN(7) |  /* 1 MHz IF filter center freq. */
                //MAX2769_CONF1_FCEN(43) | /* 2 Mhz IF filter center freq. */
                MAX2769_CONF1_FCEN(21) |   /* 4 Mhz IF filter center freq. */
                //MAX2769_CONF1_FCEN(42) | /* 8 Mhz IF filter center freq. */
                MAX2769_CONF1_FBW_2_5MHZ |
                MAX2769_CONF1_F3OR5_5 |
                MAX2769_CONF1_FCENX_BP |
                MAX2769_CONF1_FGAIN_HIGH |
                MAX2769_CONF1_LNAMODE_GATED);

  max2769_write(MAX2769_CONF2,
                //MAX2769_CONF2_IQEN |
                MAX2769_CONF2_GAINREF(170) |  /* optimal for 2 bits */
                //MAX2769_CONF2_GAINREF(82) | /* optimal for 3 bits */
                MAX2769_CONF2_AGCMODE_INDEP |
                MAX2769_CONF2_FORMAT_SIGN_MAG |
                MAX2769_CONF2_BITS_1 |
                MAX2769_CONF2_DRVCFG_CMOS |
                MAX2769_CONF2_LOEN
                );

  max2769_write(MAX2769_CONF3,
                MAX2769_CONF3_RESERVED |
                MAX2769_CONF3_GAININ(58) |
                MAX2769_CONF3_FSLOWEN |
                MAX2769_CONF3_ADCEN |
                MAX2769_CONF3_DRVEN |
                MAX2769_CONF3_FOFSTEN |
                MAX2769_CONF3_FILTEN |
                MAX2769_CONF3_FHIPEN |
                MAX2769_CONF3_PGAIEN |
  //MAX2769_CONF3_PGAQEN |
                /* STRM stuff was set before but its unused,
                 * can leave as zeros. */
                0
                );

  max2769_write(MAX2769_PLLCONF,
                MAX2769_PLLCONF_RESERVED |
                MAX2769_PLLCONF_VCOEN |
                MAX2769_PLLCONF_REFOUTEN |
                //MAX2769_PLLCONF_REFDIV_DIV_2 |  /* 8.184 MHz sample rate */
                MAX2769_PLLCONF_REFDIV_DIV_NONE | /* 16.368 MHz sample rate */
                MAX2769_PLLCONF_IXTAL_BUFF_NORMAL |
                MAX2769_PLLCONF_XTALCAP(0b10000) |
                MAX2769_PLLCONF_LDMUX(0) |
                MAX2769_PLLCONF_ICP_1MA |
                MAX2769_PLLCONF_CPTEST(0) |
                MAX2769_PLLCONF_INTPLL
                );

  max2769_write(MAX2769_DIV,
                //MAX2769_DIV_NDIV(1538) | /* 2 * 1.023 MHz IF */
                MAX2769_DIV_NDIV(1536) |  /* 4 * 1.023 MHz IF */
                MAX2769_DIV_RDIV(16)
                );

  max2769_write(MAX2769_FDIV,
                MAX2769_FDIV_RESERVED |
                MAX2769_FDIV_FDIV(0x80000)
                );

  max2769_write(MAX2769_CLK,
                MAX2769_CLK_L_CNT(1) |
                MAX2769_CLK_M_CNT(4095) |
                MAX2769_CLK_SERCLK
                );

}