static void _max77849_restore_muic_reg(struct max77849_dev *max77849)
{
pr_info("%s:Restore muic irq\n", __func__);
max77849_write_reg(max77849->muic, MAX77849_MUIC_REG_INTMASK1, 0x09);
max77849_write_reg(max77849->muic, MAX77849_MUIC_REG_INTMASK2, 0x11);
max77849_update_reg(max77849->muic, MAX77849_MUIC_REG_CDETCTRL1,
(0x01 << CHGTYPM_SHIFT), CHGTYPM_MASK);
max77849_write_reg(max77849->muic, MAX77849_MUIC_REG_CTRL4, 0x02);
max77849_muic_regdump();
}
static int max77849_restore(struct device *dev)
{
struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
struct max77849_dev *max77849 = i2c_get_clientdata(i2c);
int i;
enable_irq(max77849->irq);
#ifdef CONFIG_MUIC_RESET_PIN_ENABLE
if (muic_reset_pin)
enable_irq(max77849->irq_reset);
#endif
for (i = 0; i < ARRAY_SIZE(max77849_dumpaddr_pmic); i++)
max77849_write_reg(i2c, max77849_dumpaddr_pmic[i],
max77849->reg_pmic_dump[i]);
for (i = 0; i < ARRAY_SIZE(max77849_dumpaddr_muic); i++)
max77849_write_reg(i2c, max77849_dumpaddr_muic[i],
max77849->reg_muic_dump[i]);
return 0;
}
static int max77849_restore(struct device *dev)
{
struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
struct max77849_dev *max77849 = i2c_get_clientdata(i2c);
int i;
enable_irq(max77849->irq);
for (i = 0; i < ARRAY_SIZE(max77849_dumpaddr_pmic); i++)
max77849_write_reg(i2c, max77849_dumpaddr_pmic[i],
max77849->reg_pmic_dump[i]);
for (i = 0; i < ARRAY_SIZE(max77849_dumpaddr_muic); i++)
max77849_write_reg(i2c, max77849_dumpaddr_muic[i],
max77849->reg_muic_dump[i]);
for (i = 0; i < ARRAY_SIZE(max77849_dumpaddr_led); i++)
max77849_write_reg(i2c, max77849_dumpaddr_led[i],
max77849->reg_led_dump[i]);
return 0;
}
static void max77849_irq_sync_unlock(struct irq_data *data)
{
struct max77849_dev *max77849 = irq_get_chip_data(data->irq);
int i;
for (i = 0; i < MAX77849_IRQ_GROUP_NR; i++) {
u8 mask_reg = max77849_mask_reg[i];
struct i2c_client *i2c = get_i2c(max77849, i);
if (mask_reg == MAX77849_REG_INVALID ||
IS_ERR_OR_NULL(i2c))
continue;
max77849->irq_masks_cache[i] = max77849->irq_masks_cur[i];
max77849_write_reg(i2c, max77849_mask_reg[i],
max77849->irq_masks_cur[i]);
}
mutex_unlock(&max77849->irqlock);
}
int max77849_irq_init(struct max77849_dev *max77849)
{
int i;
int cur_irq;
int ret;
u8 i2c_data;
pr_info("func: %s, irq_gpio: %d, irq_base: %d\n", __func__,
max77849->irq_gpio, max77849->irq_base);
#ifdef CONFIG_MUIC_RESET_PIN_ENABLE
INIT_DELAYED_WORK(&muic_restore_work, max77849_restore_muic_reg);
#endif
if (!max77849->irq_gpio) {
dev_warn(max77849->dev, "No interrupt specified.\n");
max77849->irq_base = 0;
return 0;
}
if (!max77849->irq_base) {
dev_err(max77849->dev, "No interrupt base specified.\n");
return 0;
}
mutex_init(&max77849->irqlock);
max77849->irq = gpio_to_irq(max77849->irq_gpio);
ret = gpio_request(max77849->irq_gpio, "if_pmic_irq");
if (ret) {
dev_err(max77849->dev, "%s: failed requesting gpio %d\n",
__func__, max77849->irq_gpio);
return ret;
}
gpio_direction_input(max77849->irq_gpio);
gpio_free(max77849->irq_gpio);
#ifdef CONFIG_MUIC_RESET_PIN_ENABLE
if (muic_reset_pin)
{
max77849->irq_reset = gpio_to_irq(max77849->irq_reset_gpio);
ret = gpio_request(max77849->irq_reset_gpio, "muic_reset_irq");
if (ret) {
dev_err(max77849->dev, "%s: failed requesting gpio %d\n",
__func__, max77849->irq_reset_gpio);
return ret;
}
gpio_direction_input(max77849->irq_reset_gpio);
gpio_free(max77849->irq_reset_gpio);
}
#endif
/* Mask individual interrupt sources */
for (i = 0; i < MAX77849_IRQ_GROUP_NR; i++) {
struct i2c_client *i2c;
/* MUIC IRQ 0:MASK 1:NOT MASK */
/* Other IRQ 1:MASK 0:NOT MASK */
if (i >= MUIC_INT1 && i <= MUIC_INT3) {
max77849->irq_masks_cur[i] = 0x00;
max77849->irq_masks_cache[i] = 0x00;
} else {
max77849->irq_masks_cur[i] = 0xff;
max77849->irq_masks_cache[i] = 0xff;
}
i2c = get_i2c(max77849, i);
if (IS_ERR_OR_NULL(i2c))
continue;
if (max77849_mask_reg[i] == MAX77849_REG_INVALID)
continue;
if (i >= MUIC_INT1 && i <= MUIC_INT3)
max77849_write_reg(i2c, max77849_mask_reg[i], 0x00);
else
max77849_write_reg(i2c, max77849_mask_reg[i], 0xff);
}
/* Register with genirq */
for (i = 0; i < MAX77849_IRQ_NR; i++) {
cur_irq = i + max77849->irq_base;
irq_set_chip_data(cur_irq, max77849);
irq_set_chip_and_handler(cur_irq, &max77849_irq_chip,
handle_edge_irq);
irq_set_nested_thread(cur_irq, 1);
#ifdef CONFIG_ARM
set_irq_flags(cur_irq, IRQF_VALID);
#else
irq_set_noprobe(cur_irq);
#endif
}
/* Unmask max77849 interrupt */
ret = max77849_read_reg(max77849->i2c, MAX77849_PMIC_REG_INTSRC_MASK,
&i2c_data);
if (ret) {
dev_err(max77849->dev, "%s: fail to read muic reg\n", __func__);
return ret;
}
i2c_data &= ~(MAX77849_IRQSRC_CHG); /* Unmask charger interrupt */
i2c_data &= ~(MAX77849_IRQSRC_MUIC); /* Unmask muic interrupt */
max77849_write_reg(max77849->i2c, MAX77849_PMIC_REG_INTSRC_MASK,
i2c_data);
ret = request_threaded_irq(max77849->irq, NULL, max77849_irq_thread,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"max77849-irq", max77849);
if (ret) {
dev_err(max77849->dev, "Failed to request IRQ %d: %d\n",
max77849->irq, ret);
return ret;
}
#ifdef CONFIG_MUIC_RESET_PIN_ENABLE
if (muic_reset_pin)
{
ret = request_threaded_irq(max77849->irq_reset, NULL, max77849_reset_irq_thread,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"max77849-reset_irq", max77849);
if (ret) {
dev_err(max77849->dev, "Failed to request IRQ %d: %d\n",
max77849->irq_reset, ret);
return ret;
}
}
#endif
return 0;
}
static irqreturn_t max77849_irq_thread(int irq, void *data)
{
struct max77849_dev *max77849 = data;
u8 irq_reg[MAX77849_IRQ_GROUP_NR] = {0};
u8 tmp_irq_reg[MAX77849_IRQ_GROUP_NR] = {};
u8 irq_src;
int ret;
int i;
/* INTMASK1 3:ADC1K 0:ADC */
/* INTMASK2 4:VBVolt 0:Chgtype */
max77849_write_reg(max77849->muic, MAX77849_MUIC_REG_INTMASK1, 0x09);
max77849_write_reg(max77849->muic, MAX77849_MUIC_REG_INTMASK2, 0x11);
clear_retry:
ret = max77849_read_reg(max77849->i2c,
MAX77849_PMIC_REG_INTSRC, &irq_src);
if (ret < 0) {
dev_err(max77849->dev,
"Failed to read interrupt source: %d\n", ret);
return IRQ_NONE;
}
pr_info("%s: interrupt source(0x%02x)\n", __func__, irq_src);
if (irq_src & MAX77849_IRQSRC_CHG) {
/* CHG_INT */
ret = max77849_read_reg(max77849->i2c, MAX77849_CHG_REG_CHG_INT,
&irq_reg[CHG_INT]);
pr_info("%s: charger interrupt(0x%02x)\n",
__func__, irq_reg[CHG_INT]);
/* mask chgin to prevent chgin infinite interrupt
* chgin is unmasked chgin isr
*/
if (irq_reg[CHG_INT] &
max77849_irqs[MAX77849_CHG_IRQ_CHGIN_I].mask) {
u8 reg_data;
max77849_read_reg(max77849->i2c,
MAX77849_CHG_REG_CHG_INT_MASK, ®_data);
reg_data |= (1 << 6);
max77849_write_reg(max77849->i2c,
MAX77849_CHG_REG_CHG_INT_MASK, reg_data);
}
}
if (irq_src & MAX77849_IRQSRC_TOP) {
/* TOPSYS_INT */
ret = max77849_read_reg(max77849->i2c,
MAX77849_PMIC_REG_TOPSYS_INT,
&irq_reg[TOPSYS_INT]);
pr_info("%s: topsys interrupt(0x%02x)\n",
__func__, irq_reg[TOPSYS_INT]);
}
if (irq_src & MAX77849_IRQSRC_MUIC) {
/* MUIC INT1 ~ INT3 */
ret = max77849_bulk_read(max77849->muic, MAX77849_MUIC_REG_INT1,
MAX77849_NUM_IRQ_MUIC_REGS,
&tmp_irq_reg[MUIC_INT1]);
/* Or temp irq register to irq register for if it retries */
for (i = MUIC_INT1; i < MAX77849_IRQ_GROUP_NR; i++)
irq_reg[i] |= tmp_irq_reg[i];
pr_warn("%s: muic interrupt(0x%02x, 0x%02x, 0x%02x)\n",
__func__, irq_reg[MUIC_INT1],
irq_reg[MUIC_INT2], irq_reg[MUIC_INT3]);
}
pr_debug("%s: irq gpio post-state(0x%02x)\n", __func__,
gpio_get_value(max77849->irq_gpio));
if (gpio_get_value(max77849->irq_gpio) == 0) {
pr_warn("%s: irq_gpio is not High!\n", __func__);
goto clear_retry;
}
#if 0
/* Apply masking */
for (i = 0; i < MAX77849_IRQ_GROUP_NR; i++) {
if (i >= MUIC_INT1 && i <= MUIC_INT3)
irq_reg[i] &= max77849->irq_masks_cur[i];
else
irq_reg[i] &= ~max77849->irq_masks_cur[i];
}
#endif
/* Report */
for (i = 0; i < MAX77849_IRQ_NR; i++) {
if (irq_reg[max77849_irqs[i].group] & max77849_irqs[i].mask)
handle_nested_irq(max77849->irq_base + i);
}
return IRQ_HANDLED;
}