static void mdp4_dsi_cmd_overlay_nolock( struct msm_fb_data_type *mfd )
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mdp_clk_ctrl(1);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_dsi_cmd_busy();
mdp4_overlay_mdp_perf_upd(mfd, 0);
mdp_clk_ctrl(0);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on) {
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 1);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
long long xx;
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
vctrl->clk_control = 0;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit();
mdp4_dsi_cmd_wait4vsync(0, &xx);
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
vctrl->clk_control = 1;
mdp4_overlay_mdp_perf_upd(mfd, 0);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int clk_set_on = 0;
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mutex_lock(&vctrl->update_lock);
if (atomic_read(&vctrl->suspend)) {
mutex_unlock(&vctrl->update_lock);
pr_err("%s: suspended, no more pan display\n", __func__);
return;
}
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
mutex_unlock(&vctrl->update_lock);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mutex_lock(&mfd->dma->ov_mutex);
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
vctrl = &vsync_ctrl_db[cndx];
atomic_inc(&in_drawing);
if (!mfd->panel_power_on) {
atomic_dec(&in_drawing);
return;
}
pipe = vctrl->base_pipe;
if (pipe == NULL) {
atomic_dec(&in_drawing);
pr_err("%s: NO base pipe\n", __func__);
return;
}
mutex_lock(&vctrl->update_lock);
if (!vctrl->clk_enabled) {
atomic_dec(&in_drawing);
pr_err("%s: mdp clocks disabled\n", __func__);
mutex_unlock(&vctrl->update_lock);
return;
}
mutex_unlock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->expire_tick) {
/*
* in the middle of shutting clocks down
* delay to allow pan display to go through
*/
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mutex_lock(&mfd->dma->ov_mutex);
mdp4_dsi_cmd_pipe_commit();
mutex_unlock(&mfd->dma->ov_mutex);
/* mdp4_overlay_mdp_perf_upd(mfd, 0); */
atomic_dec(&in_drawing);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on) {
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
/* OPPO 2013-10-19 gousj Modify begin for WFD crash */
#ifndef CONFIG_VENDOR_EDIT
mdp4_dsi_cmd_pipe_commit(cndx, 1);
#else
mdp4_dsi_cmd_pipe_commit(cndx, 0);
#endif
/* OPPO 2013-10-19 gousj Modify end */
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_dsi_refresh_screen_at_once( struct msm_fb_data_type *mfd )
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
DISP_LOCAL_LOG_EMERG("DISP %s S\n",__func__);
if( mfd == NULL ){
return;
}
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mdp_clk_ctrl(1);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_screen_at_once_flag = 1;
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_dsi_screen_at_once_flag = 0;
mdp4_dsi_cmd_busy();
mdp4_overlay_mdp_perf_upd(mfd, 0);
mdp_clk_ctrl(0);
DISP_LOCAL_LOG_EMERG("DISP %s E\n",__func__);
return;
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int clk_set_on = 0;
#if defined(CONFIG_MACH_JAGUAR)
static int logo;
#endif
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
#if defined(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_WVGA_PT) || \
defined(CONFIG_FB_MSM_MIPI_NOVATEK_BOE_CMD_WVGA_PT)
if (!is_lcd_connected)
return;
#endif
mutex_lock(&vctrl->update_lock);
if (atomic_read(&vctrl->suspend)) {
#if defined(CONFIG_MACH_JAGUAR)
if (!logo || poweroff_charging ) {
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR,
MDP_PRIM_RDPTR_TERM);
logo = 1;
} else {
pr_err("%s: mdp clocks disabled\n", __func__);
mutex_unlock(&vctrl->update_lock);
return;
}
#else
mutex_unlock(&vctrl->update_lock);
pr_err("%s: suspended, no more pan display\n", __func__);
return;
#endif
}
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
}
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_err("%s: warning, clock off while pan display\n", __func__);
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
mutex_unlock(&vctrl->update_lock);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mutex_lock(&mfd->dma->ov_mutex);
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
#ifdef CONFIG_VENDOR_EDIT
//liuyan modify for mhl fick in playing video
long long tick;
#endif
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mutex_lock(&vctrl->update_lock);
if (!vctrl->clk_enabled) {
pr_err("%s: mdp clocks disabled\n", __func__);
mutex_unlock(&vctrl->update_lock);
return;
}
mutex_unlock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->expire_tick) {
/*
* in the middle of shutting clocks down
* delay to allow pan display to go through
*/
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mutex_lock(&mfd->dma->ov_mutex);
#ifndef CONFIG_VENDOR_EDIT
//liuyan modify for mhl fick in playing video
//mdp4_dsi_cmd_pipe_commit();
#else
mdp4_dsi_cmd_pipe_commit(cndx, 0);
#endif
mutex_unlock(&mfd->dma->ov_mutex);
#ifdef CONFIG_VENDOR_EDIT
//liuyan modify for mhl fick in playing video
mdp4_dsi_cmd_wait4vsync(cndx, &tick);
#endif
mdp4_overlay_mdp_perf_upd(mfd, 0);
}
