int mdp4_lcdc_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int cnt = 0;
vctrl = &vsync_ctrl_db[cndx];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&vctrl->update_lock);
return 0;
}
mixer = pipe->mixer_num;
mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
/*
* allow stage_commit without pipes queued
* (vp->update_cnt == 0) to unstage pipes after
* overlay_unset
*/
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done) {
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
pr_err("%s: Error, frame dropped %d %d\n", __func__,
vctrl->ov_koff, vctrl->ov_done);
return 0;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_overlay_mdp_perf_upd(vctrl->mfd, 1);
if (vctrl->blt_change) {
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
INIT_COMPLETION(vctrl->dmap_comp);
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_lcdc_wait4dmap(0);
if (pipe->ov_blt_addr)
mdp4_lcdc_wait4ov(0);
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
//yanghai add the iommu patch 2013.5.25
#ifndef CONFIG_VENDOR_EDIT
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
#endif
}
}
mdp4_mixer_stage_commit(mixer);
/* start timing generator & mmu if they are not started yet */
mdp4_overlay_lcdc_start();
//yanghai add the iommu patch 2013.5.25
#ifdef CONFIG_VENDOR_EDIT
/*
* there has possibility that pipe commit come very close to next vsync
* this may cause two consecutive pie_commits happen within same vsync
* period which casue iommu page fault when previous iommu buffer
* freed. Set ION_IOMMU_UNMAP_DELAYED flag at ion_map_iommu() to
* add delay unmap iommu buffer to fix this problem.
* Also ion_unmap_iommu() may take as long as 9 ms to free an ion buffer.
* therefore mdp4_overlay_iommu_unmap_freelist(mixer) should be called
* ater stage_commit() to ensure pipe_commit (up to stage_commit)
* is completed within vsync period.
*/
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
#endif
//yanghai add end
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_lcdc_blt_ov_update(pipe);
pipe->ov_cnt++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
mb();
vctrl->ov_koff++;
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
} else {
/* schedule second phase update at dmap */
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait) {
if (pipe->ov_blt_addr)
mdp4_lcdc_wait4ov(0);
else
mdp4_lcdc_wait4dmap(0);
}
return cnt;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int mixer = 0;
int undx, need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
/*
* Image fade away on video mode panel when suspend,
* work it around by turning off panel to hide it
*/
mdp4_dsi_panel_off(mfd);
mipi_dsi_panel_power_en(pdev, 0);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
mdp4_dsi_video_wait4vsync(cndx);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
dsi_video_enabled = 0;
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dsi_video_pipe_clean(vp);
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mixer = pipe->mixer_num;
mdp4_overlay_unset_mixer(mixer);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
mdp4_dsi_video_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
mdp4_video_vsync_irq_ctrl(cndx, 0);
}
/*
* clean up ion freelist
* there need two stage to empty ion free list
* therefore need call unmap freelist twice
*/
mdp4_overlay_iommu_unmap_freelist(mixer);
mdp4_overlay_iommu_unmap_freelist(mixer);
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mutex_unlock(&mfd->dma->ov_mutex);
return ret;
}
int mdp4_dtv_pipe_commit(void)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int cnt = 0;
vctrl = &vsync_ctrl_db[0];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
mdp4_overlay_iommu_unmap_freelist(mixer);
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return 0;
}
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0;
mutex_unlock(&vctrl->update_lock);
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
mdp4_overlay_vsync_commit(pipe);
}
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0;
}
}
mdp4_mixer_stage_commit(mixer);
mdp4_overlay_dtv_start();
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dtv_blt_ov_update(pipe);
pipe->blt_ov_done++;
vsync_irq_enable(INTR_OVERLAY1_DONE, MDP_OVERLAY1_TERM);
mb();
pipe->blt_ov_koff++;
mdp4_stat.kickoff_ov1++;
outpdw(MDP_BASE + 0x0008, 0);
} else {
INIT_COMPLETION(vctrl->dmae_comp);
vsync_irq_enable(INTR_DMA_E_DONE, MDP_DMA_E_TERM);
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
return cnt;
}
int mdp4_dsi_cmd_pipe_commit(void)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int need_dmap_wait = 0;
int need_ov_wait = 0;
int cnt = 0;
vctrl = &vsync_ctrl_db[0];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
}
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
mdp4_backlight_commit_level(vctrl);
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
/* Blt */
if (vctrl->blt_wait)
need_dmap_wait = 1;
else if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
} else {
/* direct out */
if (vctrl->dmap_koff != vctrl->dmap_done) {
INIT_COMPLETION(vctrl->dmap_comp);
pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d\n",
__func__, vctrl->ov_koff, vctrl->ov_done,
vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());
need_dmap_wait = 1;
}
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_dmap_wait) {
pr_debug("%s: wait4dmap\n", __func__);
mdp4_dsi_cmd_wait4dmap(0);
}
if (need_ov_wait) {
pr_debug("%s: wait4ov\n", __func__);
mdp4_dsi_cmd_wait4ov(0);
}
if (pipe->ov_blt_addr) {
if (vctrl->blt_end) {
vctrl->blt_end = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
}
}
if (vctrl->blt_change) {
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
vctrl->blt_change = 0;
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
mdp4_overlay_vsync_commit(pipe);
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
mdp4_mixer_stage_commit(mixer);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_cmd_blt_ov_update(pipe);
pipe->ov_cnt++;
vctrl->ov_koff++;
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
} else {
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
vctrl->dmap_koff++;
}
pr_debug("%s: kickoff\n", __func__);
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
mb(); /* make sure kickoff ececuted */
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
return cnt;
}
int mdp4_dsi_video_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int cnt = 0;
vctrl = &vsync_ctrl_db[cndx];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
}
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done) {
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
pr_err("%s: Error, frame dropped %d %d\n", __func__,
vctrl->ov_koff, vctrl->ov_done);
return 0;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (vctrl->blt_change) {
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
INIT_COMPLETION(vctrl->dmap_comp);
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_dsi_video_wait4dmap(0);
if (pipe->ov_blt_addr)
mdp4_dsi_video_wait4ov(0);
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
mdp4_mixer_stage_commit(mixer);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_video_blt_ov_update(pipe);
pipe->ov_cnt++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
mb();
vctrl->ov_koff++;
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
} else {
/* schedule second phase update at dmap */
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait) {
if (pipe->ov_blt_addr)
mdp4_dsi_video_wait4ov(cndx);
else
mdp4_dsi_video_wait4dmap(cndx);
}
return cnt;
}
int mdp4_dsi_cmd_pipe_commit(void)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int need_dmap_wait = 0;
int need_ov_wait = 0;
int cnt = 0;
vctrl = &vsync_ctrl_db[0];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
}
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0;
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
if (vctrl->blt_wait)
need_dmap_wait = 1;
if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
} else {
if (vctrl->dmap_koff != vctrl->dmap_done) {
INIT_COMPLETION(vctrl->dmap_comp);
pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d\n",
__func__, vctrl->ov_koff, vctrl->ov_done,
vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());
need_dmap_wait = 1;
}
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_dmap_wait) {
pr_debug("%s: wait4dmap\n", __func__);
mdp4_dsi_cmd_wait4dmap(0);
}
if (need_ov_wait) {
pr_debug("%s: wait4ov\n", __func__);
mdp4_dsi_cmd_wait4ov(0);
}
if (pipe->ov_blt_addr) {
if (vctrl->blt_end) {
vctrl->blt_end = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
}
}
if (vctrl->blt_change) {
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
vctrl->blt_change = 0;
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
mdp4_overlay_vsync_commit(pipe);
}
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0;
}
}
mipi_dsi_cmdlist_commit(1);
mdp4_mixer_stage_commit(mixer);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_cmd_blt_ov_update(pipe);
pipe->ov_cnt++;
vctrl->ov_koff++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
} else {
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
vctrl->dmap_koff++;
}
pr_debug("%s: kickoff, pid=%d\n", __func__, current->pid);
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
mb();
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
return cnt;
}
int mdp4_dsi_cmd_pipe_commit(int cndx, int wait)
#endif
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int need_dmap_wait = 0;
int need_ov_wait = 0;
int cnt = 0;
#ifndef CONFIG_VENDOR_EDIT
//liuyan modify for mhl fick in playing video
//vctrl = &vsync_ctrl_db[0];
#else
vctrl = &vsync_ctrl_db[cndx];
#endif
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
}
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
/* Blt */
if (vctrl->blt_wait)
need_dmap_wait = 1;
if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
} else {
/* direct out */
if (vctrl->dmap_koff != vctrl->dmap_done) {
INIT_COMPLETION(vctrl->dmap_comp);
pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d\n",
__func__, vctrl->ov_koff, vctrl->ov_done,
vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());
need_dmap_wait = 1;
}
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_dmap_wait) {
pr_debug("%s: wait4dmap\n", __func__);
mdp4_dsi_cmd_wait4dmap(0);
}
if (need_ov_wait) {
pr_debug("%s: wait4ov\n", __func__);
mdp4_dsi_cmd_wait4ov(0);
}
if (pipe->ov_blt_addr) {
if (vctrl->blt_end) {
vctrl->blt_end = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
}
}
if (vctrl->blt_change) {
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
vctrl->blt_change = 0;
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
/* tx dcs command if had any */
mipi_dsi_cmdlist_commit(1);
mdp4_mixer_stage_commit(mixer);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_cmd_blt_ov_update(pipe);
pipe->ov_cnt++;
vctrl->ov_koff++;
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
} else {
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
vctrl->dmap_koff++;
}
pr_debug("%s: kickoff\n", __func__);
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
mb();
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
#ifdef CONFIG_VENDOR_EDIT
//liuyan modify for mhl fick in playing video
if (wait) {
long long tick;
mdp4_dsi_cmd_wait4vsync(cndx, &tick);
}
#endif
return cnt;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int undx, need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
mdp4_dsi_video_wait4vsync(cndx);
atomic_set(&vctrl->vsync_resume, 0);
complete_all(&vctrl->vsync_comp);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
dsi_video_enabled = 0;
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dsi_video_pipe_clean(vp);
}
/* MM-KW-TraceLog-00+ */
printk(KERN_INFO "[DISPLAY]%s: pipe %d, cnt %d, e %d\n",
__func__, (pipe != NULL), mfd->ref_cnt, vctrl->vsync_irq_enabled);
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
mdp4_dsi_video_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
return ret;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
atomic_set(&vctrl->suspend, 1);
atomic_set(&vctrl->vsync_resume, 0);
msleep(20); /* >= 17 ms */
complete_all(&vctrl->vsync_comp);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
dsi_video_enabled = 0;
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
return ret;
}
int mdp4_dsi_cmd_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
int undx;
int need_wait, cnt;
unsigned long flags;
int mixer = 0;
pr_debug("%s+: pid=%d\n", __func__, current->pid);
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return ret;
}
need_wait = 0;
mutex_lock(&vctrl->update_lock);
complete_all(&vctrl->vsync_comp);
pr_debug("%s: clk=%d pan=%d\n", __func__,
vctrl->clk_enabled, vctrl->pan_display);
if (vctrl->clk_enabled)
need_wait = 1;
mutex_unlock(&vctrl->update_lock);
cnt = 0;
if (need_wait) {
while (vctrl->clk_enabled) {
msleep(20);
cnt++;
if (cnt > 10)
break;
}
}
if (cnt > 10) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->clk_enabled = 0;
vctrl->expire_tick = 0;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mipi_dsi_clk_cfg(0);
mdp_clk_ctrl(0);
pr_err("%s: Error, SET_CLK_OFF by force\n", __func__);
}
if (vctrl->vsync_enabled) {
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
vctrl->vsync_enabled = 0;
}
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dsi_cmd_pipe_clean(vp);
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mixer = pipe->mixer_num;
mdp4_overlay_unset_mixer(mixer);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 1);
}
}
atomic_set(&vctrl->suspend, 1);
/*
* clean up ion freelist
* there need two stage to empty ion free list
* therefore need call unmap freelist twice
*/
mdp4_overlay_iommu_unmap_freelist(mixer);
mdp4_overlay_iommu_unmap_freelist(mixer);
mutex_unlock(&mfd->dma->ov_mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
int mdp4_dsi_cmd_pipe_commit(int cndx, int wait, u32 *release_busy)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int need_dmap_wait = 0;
int need_ov_wait = 0;
int cnt = 0;
vctrl = &vsync_ctrl_db[0];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&vctrl->update_lock);
return 0;
}
mixer = pipe->mixer_num;
mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
/*
* allow stage_commit without pipes queued
* (vp->update_cnt == 0) to unstage pipes after
* overlay_unset
*/
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
if (mdp4_dsi_cmd_clk_check(vctrl) < 0) {
mdp4_dsi_cmd_pipe_clean(vp);
mutex_unlock(&vctrl->update_lock);
return 0;
}
mutex_unlock(&vctrl->update_lock);
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
/* Blt */
if (vctrl->blt_wait) {
INIT_COMPLETION(vctrl->dmap_comp);
need_dmap_wait = 1;
}
if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
} else {
/* direct out */
if (vctrl->dmap_koff != vctrl->dmap_done) {
INIT_COMPLETION(vctrl->dmap_comp);
pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d\n",
__func__, vctrl->ov_koff, vctrl->ov_done,
vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());
need_dmap_wait = 1;
}
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_dmap_wait) {
pr_debug("%s: wait4dmap\n", __func__);
mdp4_dsi_cmd_wait4dmap(0);
}
if (need_ov_wait) {
pr_debug("%s: wait4ov\n", __func__);
mdp4_dsi_cmd_wait4ov(0);
}
if (pipe->ov_blt_addr) {
if (vctrl->blt_end) {
vctrl->blt_end = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
}
}
if (vctrl->blt_change) {
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
vctrl->blt_change = 0;
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
/* tx dcs command if had any */
mipi_dsi_cmdlist_commit(1);
mdp4_mixer_stage_commit(mixer);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_cmd_blt_ov_update(pipe);
pipe->ov_cnt++;
vctrl->ov_koff++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
} else {
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
vctrl->dmap_koff++;
}
pr_debug("%s: kickoff, pid=%d\n", __func__, current->pid);
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
mb(); /* make sure kickoff ececuted */
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait) {
if (release_busy) {
msm_fb_release_busy(vctrl->mfd);
*release_busy = false;
mutex_unlock(&vctrl->mfd->dma->ov_mutex);
}
if (pipe->ov_blt_addr)
mdp4_dsi_cmd_wait4ov(0);
else
mdp4_dsi_cmd_wait4dmap(0);
}
return cnt;
}
int mdp4_dsi_cmd_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int need_dmap_wait = 0;
int need_ov_wait = 0;
int cnt = 0;
vctrl = &vsync_ctrl_db[0];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
}
#ifdef CONFIG_HW_ESD_DETECT
/*add qcom patch to solve esd issue*/
if (vctrl->mfd->is_panel_alive == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
}
#endif
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
/* Blt */
if (vctrl->blt_wait)
need_dmap_wait = 1;
if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
} else {
/* direct out */
if (vctrl->dmap_koff != vctrl->dmap_done) {
INIT_COMPLETION(vctrl->dmap_comp);
pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d\n",
__func__, vctrl->ov_koff, vctrl->ov_done,
vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());
need_dmap_wait = 1;
}
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_dmap_wait) {
pr_debug("%s: wait4dmap\n", __func__);
mdp4_dsi_cmd_wait4dmap(0);
}
if (need_ov_wait) {
pr_debug("%s: wait4ov\n", __func__);
mdp4_dsi_cmd_wait4ov(0);
}
if (pipe->ov_blt_addr) {
if (vctrl->blt_end) {
vctrl->blt_end = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
}
}
if (vctrl->blt_change) {
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
vctrl->blt_change = 0;
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
/* tx dcs command if had any */
/*fix qcom command list bug*/
#ifdef CONFIG_HUAWEI_KERNEL
mutex_lock(&cmd_mutex);
#endif
mipi_dsi_cmdlist_commit(1);
#ifdef CONFIG_HUAWEI_KERNEL
mutex_unlock(&cmd_mutex);
#endif
mdp4_mixer_stage_commit(mixer);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_cmd_blt_ov_update(pipe);
pipe->ov_cnt++;
vctrl->ov_koff++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
} else {
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
vctrl->dmap_koff++;
}
pr_debug("%s: kickoff, pid=%d\n", __func__, current->pid);
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
mdp_pipe_kickoff_simplified(MDP_OVERLAY0_TERM);
mb(); /* make sure kickoff ececuted */
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait)
mdp4_dsi_cmd_wait4vsync(0);
return cnt;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int undx, need_wait = 0;
#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_FHD_INVERSE_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_FHD_INVERSE_PT_PANEL)
int retry_cnt = 0;
#endif
printk(KERN_INFO "[LCD][DEBUG] %s is started.. \n", __func__);
#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_FHD_INVERSE_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_FHD_INVERSE_PT_PANEL)
do {
ret = mipi_lgit_lcd_off(pdev);
if (ret < 0) {
panel_next_off(pdev);
msleep(2);
panel_next_on(pdev);
msleep(5);
retry_cnt++;
}
else
{
// if upper routine is successed, need to initialize ret variable.
ret = 0;
break;
}
} while(retry_cnt < 10);
printk(KERN_INFO "[LCD][DEBUG] %s : mipi_lgit_lcd_off retry_cnt = %d\n", __func__, retry_cnt);
#endif
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
atomic_set(&vctrl->suspend, 1);
atomic_set(&vctrl->vsync_resume, 0);
msleep(20); /* >= 17 ms */
if (vctrl->wait_vsync_cnt) {
complete_all(&vctrl->vsync_comp);
vctrl->wait_vsync_cnt = 0;
}
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
dsi_video_enabled = 0;
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
}
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
vp->update_cnt = 0; /* empty queue */
}
mutex_lock(&mfd->dma->ov_mutex);
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mutex_unlock(&mfd->dma->ov_mutex);
printk(KERN_INFO "[LCD][DEBUG] %s is ended.. \n", __func__);
return ret;
}
int mdp4_lcdc_pipe_commit(void)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int cnt = 0;
vctrl = &vsync_ctrl_db[0];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return 0;
}
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0;
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done) {
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
pr_err("%s: Error, frame dropped %d %d\n", __func__,
vctrl->ov_koff, vctrl->ov_done);
return 0;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_overlay_mdp_perf_upd(vctrl->mfd, 1);
if (vctrl->blt_change) {
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
INIT_COMPLETION(vctrl->dmap_comp);
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_lcdc_wait4dmap(0);
if (pipe->ov_blt_addr)
mdp4_lcdc_wait4ov(0);
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
mdp4_overlay_vsync_commit(pipe);
}
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0;
}
}
mdp4_mixer_stage_commit(mixer);
mdp4_overlay_lcdc_start();
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_lcdc_blt_ov_update(pipe);
pipe->ov_cnt++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
mb();
vctrl->ov_koff++;
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
} else {
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
return cnt;
}
int mdp4_lcdc_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int undx, need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
mdp4_lcdc_wait4vsync(cndx);
atomic_set(&vctrl->vsync_resume, 0);
complete_all(&vctrl->vsync_comp);
//yanghai add the iommu patch 2013.5.25
#ifdef CONFIG_VENDOR_EDIT
vctrl->wait_vsync_cnt = 0;
#endif
//yanghai add end
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_lcdc_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
lcdc_enabled = 0;
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_lcdc_pipe_clean(vp);
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
mdp4_lcdc_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
/* MDP clock disable */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mutex_unlock(&mfd->dma->ov_mutex);
return ret;
}
int mdp4_lcdc_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int undx, need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
atomic_set(&vctrl->suspend, 1);
atomic_set(&vctrl->vsync_resume, 0);
msleep(20); /* >= 17 ms */
complete_all(&vctrl->vsync_comp);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_lcdc_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
MDP_OUTP(MDP_BASE + LCDC_BASE, 0);
lcdc_enabled = 0;
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
}
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
vp->update_cnt = 0; /* empty queue */
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
/* MDP clock disable */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
return ret;
}
int mdp4_dtv_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int cnt = 0;
vctrl = &vsync_ctrl_db[cndx];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
mdp4_overlay_iommu_unmap_freelist(mixer);
mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
/*
* allow stage_commit without pipes queued
* (vp->update_cnt == 0) to unstage pipes after
* overlay_unset
*/
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return 0;
}
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
mutex_unlock(&vctrl->update_lock);
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
mdp4_mixer_stage_commit(mixer);
/* start timing generator & mmu if they are not started yet */
mdp4_overlay_dtv_start();
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dtv_blt_ov_update(pipe);
pipe->blt_ov_done++;
vsync_irq_enable(INTR_OVERLAY1_DONE, MDP_OVERLAY1_TERM);
mb();
pipe->blt_ov_koff++;
/* kickoff overlay1 engine */
mdp4_stat.kickoff_ov1++;
outpdw(MDP_BASE + 0x0008, 0);
} else {
/* schedule second phase update at dmap */
INIT_COMPLETION(vctrl->dmae_comp);
vsync_irq_enable(INTR_DMA_E_DONE, MDP_DMA_E_TERM);
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait)
mdp4_dtv_wait4dmae(0);
return cnt;
}
int mdp4_mddi_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int need_dmap_wait = 0;
int need_ov_wait = 0;
int cnt = 0, clk_set_on = 0;
vctrl = &vsync_ctrl_db[0];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
}
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_debug("%s: SET_CLK_ON\n", __func__);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(MDP4_MIXER0);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
/* Blt */
if (vctrl->blt_wait) {
INIT_COMPLETION(vctrl->dmap_comp);
need_dmap_wait = 1;
}
if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
} else {
/* direct out */
if (vctrl->dmap_koff != vctrl->dmap_done) {
INIT_COMPLETION(vctrl->dmap_comp);
pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d\n",
__func__, vctrl->ov_koff, vctrl->ov_done,
vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());
need_dmap_wait = 1;
}
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_dmap_wait) {
pr_debug("%s: wait4dmap\n", __func__);
mdp4_mddi_wait4dmap(0);
}
if (need_ov_wait) {
pr_debug("%s: wait4ov\n", __func__);
mdp4_mddi_wait4ov(0);
}
if (pipe->ov_blt_addr) {
if (vctrl->blt_end) {
vctrl->blt_end = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
}
}
if (vctrl->blt_change) {
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
vctrl->blt_change = 0;
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
mdp4_mixer_stage_commit(MDP4_MIXER0);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_mddi_blt_ov_update(pipe);
pipe->ov_cnt++;
vctrl->ov_koff++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
} else {
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
vctrl->dmap_koff++;
}
pr_debug("%s: kickoff, pid=%d\n", __func__, current->pid);
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
mb(); /* make sure kickoff ececuted */
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait) {
if (pipe->ov_blt_addr)
mdp4_mddi_wait4ov(0);
else
mdp4_mddi_wait4dmap(0);
}
return cnt;
}