int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ret;
dprintf(SPEW, "%s: target_panel_clock\n", __func__);
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clock_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(0);
return ret;
}
edp_clk_enable();
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
edp_clk_disable();
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);
}
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
uint32_t dual_dsi = pinfo->mipi.dual_dsi;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable(dual_dsi);
mdp_clock_disable(dual_dsi);
}
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
int32_t ret = 0;
struct mdss_dsi_pll_config *pll_data;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
pll_data->vco_delay = VCO_DELAY_USEC;
if (enable) {
mdp_gdsc_ctrl(enable);
mdss_bus_clocks_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mdss_bus_clocks_disable();
mdp_gdsc_ctrl(0);
return ret;
}
mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE);
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
if (!dsi_pll_enable_seq_8916(DSI0_PLL_BASE))
dprintf(CRITICAL, "Not able to enable the pll\n");
gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
gcc_dsi_clocks_disable(pinfo->mipi.dual_dsi);
mdp_clock_disable();
mdss_bus_clocks_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
static int msm7627a_mdp_clock_init(int enable)
{
int ret = 0;
unsigned rate = 0;
rate = panel.panel_info.clk_rate;
if (enable)
mdp_clock_init(rate);
else
mdp_clock_disable();
return ret;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
int32_t ret;
struct mdss_dsi_pll_config *pll_data;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clocks_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mmss_bus_clocks_disable();
mdp_gdsc_ctrl(0);
return ret;
}
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
mmss_dsi_clocks_disable();
mdp_clock_disable();
mmss_bus_clocks_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
static int msm8974_mdss_edp_panel_clock(int enable)
{
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
edp_clk_enable();
} else if (!target_cont_splash_screen()) {
/* Add here for continuous splash */
edp_clk_disable();
mdp_clock_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
static int msm7627a_mdp_clock_init(int enable)
{
int ret = 0;
unsigned rate = 0;
rate = panel.panel_info.clk_rate;
if (enable) {
/* enable MDP clock in MP to boost display up */
if (board_machtype() != MSM8X25_QRD5
&& board_machtype() != MSM8X25Q_SKUD)
mdp_clock_init(rate);
} else {
mdp_clock_disable();
}
return ret;
}
int target_backlight_ctrl(uint8_t enable)
{
struct pm8x41_gpio pwmgpio_param = {
.direction = PM_GPIO_DIR_OUT,
.function = PM_GPIO_FUNC_1,
.vin_sel = 2, /* VIN_2 */
.pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = 0x03,
};
if (enable) {
pm8x41_gpio_config(7, &pwmgpio_param);
/* lpg channel 2 */
pm8x41_lpg_write(3, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
pm8x41_lpg_write(3, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
pm8x41_lpg_write(3, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
pm8x41_lpg_write(3, 0x44, 0xcc); /* LPG_VALUE_LSB */
pm8x41_lpg_write(3, 0x45, 0x00); /* LPG_VALUE_MSB */
pm8x41_lpg_write(3, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
} else {
pm8x41_lpg_write(3, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
}
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
uint32_t dual_dsi = pinfo->mipi.dual_dsi;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clock_enable();
mdp_clock_enable();
mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi &&
!(pinfo->mipi.broadcast)) {
mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
dsi_pll_enable_seq(MIPI_DSI1_BASE);
}
mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
mmss_dsi_clock_disable(dual_dsi);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);
}
return NO_ERROR;
}
/* Pull DISP_RST_N high to get panel out of reset */
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo)
{
uint32_t i = 0;
if (enable) {
gpio_tlmm_config(reset_gpio.pin_id, 0,
reset_gpio.pin_direction, reset_gpio.pin_pull,
reset_gpio.pin_strength, reset_gpio.pin_state);
gpio_tlmm_config(enable_gpio.pin_id, 0,
enable_gpio.pin_direction, enable_gpio.pin_pull,
enable_gpio.pin_strength, enable_gpio.pin_state);
gpio_tlmm_config(bkl_gpio.pin_id, 0,
bkl_gpio.pin_direction, bkl_gpio.pin_pull,
bkl_gpio.pin_strength, bkl_gpio.pin_state);
gpio_set(enable_gpio.pin_id, 2);
gpio_set(bkl_gpio.pin_id, 2);
/* reset */
for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
if (resetseq->pin_state[i] == GPIO_STATE_LOW)
gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
else
gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
mdelay(resetseq->sleep[i]);
}
} else {
gpio_set(reset_gpio.pin_id, 0);
gpio_set(enable_gpio.pin_id, 0);
gpio_set(bkl_gpio.pin_id, 0);
}
return NO_ERROR;
}
static int msm8974_backlight_on()
{
static struct pm8x41_wled_data wled_ctrl = {
.mod_scheme = 0xC3,
.led1_brightness = (0x0F << 8) | 0xEF,
.led2_brightness = (0x0F << 8) | 0xEF,
.led3_brightness = (0x0F << 8) | 0xEF,
.max_duty_cycle = 0x01,
};
pm8x41_wled_config(&wled_ctrl);
pm8x41_wled_sink_control(1);
pm8x41_wled_iled_sync_control(1);
pm8x41_wled_enable(1);
return 0;
}
static int msm8974_mdss_dsi_panel_clock(uint8_t enable)
{
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
mdss_dsi_uniphy_pll_config();
mmss_clock_init();
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable();
mdp_clock_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
/* Pull DISP_RST_N high to get panel out of reset */
static void msm8974_mdss_mipi_panel_reset(uint8_t enable)
{
struct pm8x41_gpio gpio19_param = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = PM_GPIO_OUT_DRIVE_MED,
};
pm8x41_gpio_config(19, &gpio19_param);
if (enable) {
gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
pm8x41_gpio_set(19, PM_GPIO_FUNC_HIGH);
mdelay(2);
pm8x41_gpio_set(19, PM_GPIO_FUNC_LOW);
mdelay(5);
pm8x41_gpio_set(19, PM_GPIO_FUNC_HIGH);
mdelay(2);
gpio_set(58, 2);
} else {
gpio19_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
pm8x41_gpio_config(19, &gpio19_param);
pm8x41_gpio_set(19, PM_GPIO_FUNC_LOW);
gpio_set(58, 2);
}
}
static int msm8974_mipi_panel_power(uint8_t enable)
{
if (enable) {
/* Enable backlight */
msm8974_backlight_on();
/* Turn on LDO8 for lcd1 mipi vdd */
dprintf(SPEW, " Setting LDO22\n");
pm8x41_ldo_set_voltage("LDO22", 3000000);
pm8x41_ldo_control("LDO22", enable);
dprintf(SPEW, " Setting LDO12\n");
/* Turn on LDO23 for lcd1 mipi vddio */
pm8x41_ldo_set_voltage("LDO12", 1800000);
pm8x41_ldo_control("LDO12", enable);
dprintf(SPEW, " Setting LDO2\n");
/* Turn on LDO2 for vdda_mipi_dsi */
pm8x41_ldo_set_voltage("LDO2", 1200000);
pm8x41_ldo_control("LDO2", enable);
dprintf(SPEW, " Panel Reset \n");
/* Panel Reset */
msm8974_mdss_mipi_panel_reset(enable);
dprintf(SPEW, " Panel Reset Done\n");
} else {
msm8974_mdss_mipi_panel_reset(enable);
pm8x41_wled_enable(enable);
pm8x41_ldo_control("LDO2", enable);
pm8x41_ldo_control("LDO22", enable);
}
return 0;
}
void display_init(void)
{
uint32_t hw_id = board_hardware_id();
uint32_t soc_ver = board_soc_version();
dprintf(INFO, "display_init(),target_id=%d.\n", hw_id);
switch (hw_id) {
case HW_PLATFORM_MTP:
case HW_PLATFORM_FLUID:
case HW_PLATFORM_SURF:
mipi_toshiba_video_720p_init(&(panel.panel_info));
panel.clk_func = msm8974_mdss_dsi_panel_clock;
panel.power_func = msm8974_mipi_panel_power;
panel.fb.base = MIPI_FB_ADDR;
panel.fb.width = panel.panel_info.xres;
panel.fb.height = panel.panel_info.yres;
panel.fb.stride = panel.panel_info.xres;
panel.fb.bpp = panel.panel_info.bpp;
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_50;
break;
default:
return;
};
if (msm_display_init(&panel)) {
dprintf(CRITICAL, "Display init failed!\n");
return;
}
display_enable = 1;
}
int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
{
struct pm8x41_gpio pwmgpio_param = {
.direction = PM_GPIO_DIR_OUT,
.function = PM_GPIO_FUNC_1,
.vin_sel = 2, /* VIN_2 */
.pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = 0x03,
};
if (enable) {
pm8x41_gpio_config(pwm_gpio.pin_id, &pwmgpio_param);
/* lpg channel 3 */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x44, 0xcc); /* LPG_VALUE_LSB */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x45, 0x00); /* LPG_VALUE_MSB */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
} else {
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
}
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ret;
struct mdss_dsi_pll_config *pll_data;
uint32_t dual_dsi = pinfo->mipi.dual_dsi;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clock_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(0);
return ret;
}
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
mmss_dsi_clock_disable(dual_dsi);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);
}
return NO_ERROR;
}