void mdss_dsi_phy_contention_detection(
struct mipi_panel_info *mipi,
uint32_t phy_base)
{
struct mdss_dsi_phy_ctrl *pd;
if ((mipi->mdss_dsi_phy_db->pll_type == DSI_PLL_TYPE_THULIUM) ||
(mdp_get_revision() == MDP_REV_304))
return;
pd = (mipi->mdss_dsi_phy_db);
writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
dmb();
}
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
unsigned long hsync_period;
unsigned long vsync_period;
unsigned long vsync_period_intmd;
struct lcdc_panel_info *lcdc = NULL;
int ystride = 3;
int mdp_rev = mdp_get_revision();
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
dprintf(SPEW, "MDP3.0.3 for DSI Video Mode\n");
hsync_period = pinfo->xres + lcdc->h_front_porch + \
lcdc->h_back_porch + 1;
vsync_period_intmd = pinfo->yres + lcdc->v_front_porch + \
lcdc->v_back_porch + 1;
if (mdp_rev == MDP_REV_304 || mdp_rev == MDP_REV_305) {
hsync_period += lcdc->h_pulse_width - 1;
vsync_period_intmd += lcdc->v_pulse_width - 1;
}
vsync_period = vsync_period_intmd * hsync_period;
// ------------- programming MDP_DMA_P_CONFIG ---------------------
writel(0x1800bf, MDP_DMA_P_CONFIG); // rgb888
writel(0x00000000, MDP_DMA_P_OUT_XY);
writel(pinfo->yres << 16 | pinfo->xres, MDP_DMA_P_SIZE);
writel(MIPI_FB_ADDR, MDP_DMA_P_BUF_ADDR);
writel(pinfo->xres * ystride, MDP_DMA_P_BUF_Y_STRIDE);
writel(hsync_period << 16 | lcdc->h_pulse_width, \
MDP_DSI_VIDEO_HSYNC_CTL);
writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
writel(lcdc->v_pulse_width * hsync_period, \
MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
if (mdp_rev == MDP_REV_304 || mdp_rev == MDP_REV_305) {
writel((pinfo->xres + lcdc->h_back_porch + \
lcdc->h_pulse_width - 1) << 16 | \
(lcdc->h_back_porch + lcdc->h_pulse_width), \
MDP_DSI_VIDEO_DISPLAY_HCTL);
writel((lcdc->v_back_porch + lcdc->v_pulse_width) \
* hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
writel(vsync_period - lcdc->v_front_porch * hsync_period - 1,
MDP_DSI_VIDEO_DISPLAY_V_END);
} else {
writel((pinfo->xres + lcdc->h_back_porch - 1) << 16 | \
lcdc->h_back_porch, MDP_DSI_VIDEO_DISPLAY_HCTL);
writel(lcdc->v_back_porch * hsync_period, \
MDP_DSI_VIDEO_DISPLAY_V_START);
writel((pinfo->yres + lcdc->v_back_porch) * hsync_period,
MDP_DSI_VIDEO_DISPLAY_V_END);
}
writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
// end of cmd mdp
return 0;
}
int mdss_dsi_video_mode_config(uint16_t disp_width,
uint16_t disp_height,
uint16_t img_width,
uint16_t img_height,
uint16_t hsync_porch0_fp,
uint16_t hsync_porch0_bp,
uint16_t vsync_porch0_fp,
uint16_t vsync_porch0_bp,
uint16_t hsync_width,
uint16_t vsync_width,
uint16_t dst_format,
uint16_t traffic_mode,
uint8_t lane_en,
uint8_t pulse_mode_hsa_he,
uint32_t low_pwr_stop_mode,
uint8_t eof_bllp_pwr,
uint8_t interleav,
uint32_t ctl_base)
{
int status = 0;
#if (DISPLAY_TYPE_MDSS == 1)
int last_line_interleave_en = 0;
/*Check if EOF_BLLP_PWR_MODE bit is set*/
if(eof_bllp_pwr & 0x8)
last_line_interleave_en = 1;
writel(0x00000000, ctl_base + CLK_CTRL);
writel(0x00000002, ctl_base + CLK_CTRL);
writel(0x00000006, ctl_base + CLK_CTRL);
writel(0x0000000e, ctl_base + CLK_CTRL);
writel(0x0000001e, ctl_base + CLK_CTRL);
writel(0x0000023f, ctl_base + CLK_CTRL);
writel(0x03f03fe0, ctl_base + ERR_INT_MASK0);
writel(0x02020202, ctl_base + INT_CTRL);
/* For 8916/8939, enable DSI timing double buffering */
if (readl(ctl_base) >= DSI_HW_REV_103 &&
mdp_get_revision() != MDP_REV_305)
writel(0x1, ctl_base + TIMING_DB_MODE);
writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
ctl_base + VIDEO_MODE_ACTIVE_H);
writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
ctl_base + VIDEO_MODE_ACTIVE_V);
if (mdp_get_revision() >= MDP_REV_41 ||
mdp_get_revision() == MDP_REV_304 ||
mdp_get_revision() == MDP_REV_305) {
writel(((disp_height + vsync_porch0_fp
+ vsync_porch0_bp - 1) << 16)
| (disp_width + hsync_porch0_fp
+ hsync_porch0_bp - 1),
ctl_base + VIDEO_MODE_TOTAL);
} else {
writel(((disp_height + vsync_porch0_fp
+ vsync_porch0_bp) << 16)
| (disp_width + hsync_porch0_fp
+ hsync_porch0_bp),
ctl_base + VIDEO_MODE_TOTAL);
}
writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC);
writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC);
writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS);
/* For 8916/8939, flush the DSI timing registers */
if (readl(ctl_base) >= DSI_HW_REV_103 &&
mdp_get_revision() != MDP_REV_305)
writel(0x1, ctl_base + TIMING_FLUSH);
writel(0x0, ctl_base + EOT_PACKET_CTRL);
writel(0x00000100, ctl_base + MISR_VIDEO_CTRL);
if (mdp_get_revision() >= MDP_REV_41 || mdp_get_revision() == MDP_REV_305) {
writel(last_line_interleave_en << 31 | pulse_mode_hsa_he << 28 |
low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 |
traffic_mode << 8 | dst_format << 4 | 0x0,
ctl_base + VIDEO_MODE_CTRL);
} else {
writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
eof_bllp_pwr << 12 | traffic_mode << 8
| dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL);
}
writel(0x3fd08, ctl_base + HS_TIMER_CTRL);
writel(0x00010100, ctl_base + MISR_VIDEO_CTRL);
writel(0x00010100, ctl_base + INT_CTRL);
writel(0x02010202, ctl_base + INT_CTRL);
writel(0x02030303, ctl_base + INT_CTRL);
writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
| 0x103, ctl_base + CTRL);
#endif
return status;
}
int mdp_lcdc_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
unsigned mdp_rgb_size;
unsigned mdp_rgb_size_src;
int hsync_period, vsync_period;
int hsync_start_x, hsync_end_x;
int display_hctl, display_vstart, display_vend;
unsigned mdp_rgb_format = 0;
int active_x, active_y;
int active_hstart_x, active_hend_x;
int active_vstart, active_vend;
int mdp_rev;
struct lcdc_panel_info *lcdc = NULL;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
mdp_rev = mdp_get_revision();
mdp_rgb_size = (pinfo->yres << 16) + pinfo->xres;
mdp_rgb_size_src = (fb->height << 16) + fb->width;
dprintf(INFO, "Panel is %d x %d\n",
pinfo->xres + lcdc->xres_pad,
pinfo->yres + lcdc->yres_pad);
/* write fb addr in MDP_DMA_P_BUF_ADDR */
writel((int)fb->base, MDP_DMA_P_BUF_ADDR);
/* write active region size*/
writel(mdp_rgb_size, MDP_DMA_P_SIZE);
/* set Y-stride value in bytes */
/* Y-stride is defined as the number of bytes
in a line.
*/
writel((pinfo->xres * pinfo->bpp/8), MDP_DMA_P_BUF_Y_STRIDE);
/* Start XY coordinates */
writel(0, MDP_DMA_P_OUT_XY);
if (fb->bpp == 16) {
writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB |
DMA_DITHER_EN | DMA_OUT_SEL_LCDC |
DMA_IBUF_FORMAT_RGB565 | DMA_DSTC0G_6BITS |
DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS,
MDP_DMA_P_CONFIG);
mdp_rgb_format = MDP_RGB_565_FORMAT;
} else if (fb->bpp == 24) {
writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB |
DMA_DITHER_EN | DMA_OUT_SEL_LCDC |
DMA_IBUF_FORMAT_RGB888 | DMA_DSTC0G_8BITS |
DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS,
MDP_DMA_P_CONFIG);
mdp_rgb_format = MDP_RGB_888_FORMAT;
} else {
dprintf(CRITICAL, "Unsupported bpp detected!\n");
return ERR_INVALID_ARGS;
}
hsync_period = lcdc->h_pulse_width +
lcdc->h_back_porch +
pinfo->xres + lcdc->h_front_porch;
vsync_period = (lcdc->v_pulse_width +
lcdc->v_back_porch +
pinfo->yres +
lcdc->v_front_porch) *
hsync_period;
hsync_start_x =
lcdc->h_pulse_width +
lcdc->h_back_porch;
hsync_end_x =
hsync_period - lcdc->h_front_porch - 1;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
display_vstart = (lcdc->v_pulse_width +
lcdc->v_back_porch)
* hsync_period + lcdc->hsync_skew;
display_vend = vsync_period -
(lcdc->v_front_porch * hsync_period)
+lcdc->hsync_skew - 1;
active_x = (pinfo->xres - fb->width)/2;
active_y = (pinfo->yres - fb->height)/2;
active_hstart_x = lcdc->h_pulse_width + lcdc->h_back_porch
+ active_x;
active_hend_x = active_hstart_x + fb->width - 1;
active_vstart = (lcdc->v_pulse_width + lcdc->v_back_porch
+ active_y) * hsync_period
+ lcdc->hsync_skew;
active_vend = active_vstart + (fb->height * hsync_period) - 1;
/* LCDC specific initalizations */
writel((hsync_period << 16) | lcdc->h_pulse_width,
MDP_LCDC_HSYNC_CTL);
writel(vsync_period, MDP_LCDC_VSYNC_PERIOD);
writel(lcdc->v_pulse_width * hsync_period,
MDP_LCDC_VSYNC_PULSE_WIDTH);
writel(display_hctl, MDP_LCDC_DISPLAY_HCTL);
writel(display_vstart, MDP_LCDC_DISPLAY_V_START);
writel(display_vend, MDP_LCDC_DISPLAY_V_END);
if (mdp_rev >= MDP_REV_40) {
writel(BIT(31) | (active_hend_x << 16) | active_hstart_x,
MDP_LCDC_ACTIVE_HCTL);
writel(BIT(31) | active_vstart, MDP_LCDC_ACTIVE_V_START);
writel(active_vend, MDP_LCDC_ACTIVE_V_END);
writel(0xf, MDP_LCDC_BORDER_CLR);
writel(0xff, MDP_LCDC_UNDERFLOW_CTL);
writel(lcdc->hsync_skew,
MDP_LCDC_HSYNC_SKEW);
writel(0x3, MDP_LCDC_CTL_POLARITY);
writel(0, MDP_LCDC_ACTIVE_HCTL);
writel(0, MDP_LCDC_ACTIVE_V_START);
writel(0, MDP_LCDC_ACTIVE_V_END);
/* setting for single layer direct out mode for rgb565 source */
writel(0x100, MDP_LAYERMIXER_IN_CFG);
writel(mdp_rgb_size_src, MDP_RGB1_SRC_SIZE);
writel(mdp_rgb_size, MDP_RGB1_OUT_SIZE);
writel((int)fb->base, MDP_RGB1_SRCP0_ADDR);
writel((fb->stride * fb->bpp / 8), MDP_RGB1_SRC_YSTRIDE1);
writel(0x00, MDP_RGB1_CONSTANT_COLOR);
writel(mdp_rgb_format, MDP_RGB1_SRC_FORMAT);
writel(0x1, MDP_OVERLAYPROC0_CFG);
if (fb->bpp == 16)
writel(0x1, MDP_OVERLAYPROC0_OPMODE);
else if (fb->bpp == 24)
writel(0x0, MDP_OVERLAYPROC0_OPMODE);
/* register flush and enable LCDC */
writel(0x11, MDP_OVERLAY_REG_FLUSH);
} else if (MDP_REV_303 == mdp_rev) {
writel(0x0, MDP_BASE + LCDC_BASE + 0x28);
writel(0xff, MDP_BASE + LCDC_BASE + 0x2c);
writel(lcdc->hsync_skew, MDP_BASE + LCDC_BASE + 0x30);
writel(0x0, MDP_BASE + LCDC_BASE + 0x38);
writel(0x0, MDP_BASE + LCDC_BASE + 0x1c);
writel(0x0, MDP_BASE + LCDC_BASE + 0x20);
writel(0x0, MDP_BASE + LCDC_BASE + 0x24);
}
return NO_ERROR;
}
static int mdss_dsi_phy_28nm_init(struct mipi_panel_info *mipi,
uint32_t ctl_base, uint32_t phy_base, uint32_t reg_base)
{
struct mdss_dsi_phy_ctrl *pd;
uint32_t i, off = 0, ln, offset, dsi0_phy_base;
if (mdp_get_revision() == MDP_REV_304)
return mdss_dsi_v2_phy_init(mipi, ctl_base);
pd = (mipi->mdss_dsi_phy_db);
/* PHY_CTRL_0 */
writel(0x5b, phy_base + 0x0170);
/* Strength ctrl 0 */
writel(pd->strength[0], phy_base + 0x0184);
mdss_dsi_phy_regulator_init(pd, ctl_base, phy_base, reg_base);
off = 0x0140; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
writel(pd->timing[i], phy_base + off);
dmb();
off += 4;
}
/* 4 lanes + clk lane configuration */
/* lane config n * (0 - 4) & DataPath setup */
for (ln = 0; ln < 5; ln++) {
off = (ln * 0x40);
for (i = 0; i < 9; i++) {
offset = i + (ln * 9);
writel(pd->laneCfg[offset], phy_base + off);
dmb();
off += 4;
}
}
/* MMSS_DSI_0_PHY_DSIPHY_CTRL_4 */
writel(0x0a, phy_base + 0x0180);
dmb();
/* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */
if (mipi->dual_dsi) {
dsi0_phy_base = DSI0_PHY_BASE +
target_display_get_base_offset(DSI0_PHY_BASE);
if ((phy_base == dsi0_phy_base) ||
(readl(mipi->ctl_base) == DSI_HW_REV_103_1))
writel(0x01, phy_base + 0x01d4);
else
writel(0x00, phy_base + 0x01d4);
} else {
writel(0x01, phy_base + 0x01d4);
}
dmb();
/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
writel(0x5f, phy_base + 0x0170);
dmb();
off = 0x01b4; /* phy BIST ctrl 0 - 5 */
for (i = 0; i < 6; i++) {
writel(pd->bistCtrl[i], phy_base + off);
off += 4;
}
dmb();
/* DSI_0_CLKOUT_TIMING_CTRL */
writel(0x41b, ctl_base + 0x0c4);
dmb();
return 0;
}
int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo)
{
struct mipi_dsi_phy_ctrl *pd;
uint32_t i, off = 0;
int mdp_rev;
mdp_rev = mdp_get_revision();
if (MDP_REV_303 == mdp_rev || MDP_REV_41 == mdp_rev) {
writel(0x00000001, DSIPHY_SW_RESET);
writel(0x00000000, DSIPHY_SW_RESET);
pd = (pinfo->dsi_phy_config);
off = 0x02cc; /* regulator ctrl 0 */
for (i = 0; i < 4; i++) {
writel(pd->regulator[i], MIPI_DSI_BASE + off);
off += 4;
}
off = 0x0260; /* phy timig ctrl 0 */
for (i = 0; i < 11; i++) {
writel(pd->timing[i], MIPI_DSI_BASE + off);
off += 4;
}
/* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing
length should > data lane HS timing length */
writel(0xa1e, DSI_CLKOUT_TIMING_CTRL);
off = 0x0290; /* ctrl 0 */
for (i = 0; i < 4; i++) {
writel(pd->ctrl[i], MIPI_DSI_BASE + off);
off += 4;
}
off = 0x02a0; /* strength 0 */
for (i = 0; i < 4; i++) {
writel(pd->strength[i], MIPI_DSI_BASE + off);
off += 4;
}
if (1 == pinfo->num_of_lanes)
pd->pll[10] |= 0x8;
off = 0x0204; /* pll ctrl 1, skip 0 */
for (i = 1; i < 21; i++) {
writel(pd->pll[i], MIPI_DSI_BASE + off);
off += 4;
}
/* pll ctrl 0 */
writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
/* lane swp ctrol */
if (pinfo->lane_swap)
writel(pinfo->lane_swap, MIPI_DSI_BASE + 0xac);
} else {
writel(0x0001, MIPI_DSI_BASE + 0x128); /* start phy sw reset */
writel(0x0000, MIPI_DSI_BASE + 0x128); /* end phy w reset */
writel(0x0003, MIPI_DSI_BASE + 0x500); /* regulator_ctrl_0 */
writel(0x0001, MIPI_DSI_BASE + 0x504); /* regulator_ctrl_1 */
writel(0x0001, MIPI_DSI_BASE + 0x508); /* regulator_ctrl_2 */
writel(0x0000, MIPI_DSI_BASE + 0x50c); /* regulator_ctrl_3 */
writel(0x0100, MIPI_DSI_BASE + 0x510); /* regulator_ctrl_4 */
pd = (pinfo->dsi_phy_config);
off = 0x0480; /* strength 0 - 2 */
for (i = 0; i < 3; i++) {
writel(pd->strength[i], MIPI_DSI_BASE + off);
off += 4;
}
off = 0x0470; /* ctrl 0 - 3 */
for (i = 0; i < 4; i++) {
writel(pd->ctrl[i], MIPI_DSI_BASE + off);
off += 4;
}
off = 0x0500; /* regulator ctrl 0 - 4 */
for (i = 0; i < 5; i++) {
writel(pd->regulator[i], MIPI_DSI_BASE + off);
off += 4;
}
mipi_dsi_calibration(MIPI_DSI_BASE);
off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
for (i = 1; i < 20; i++) {
writel(pd->pll[i], MIPI_DSI_BASE + off);
off += 4;
}
/* pll ctrl 0 */
writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
/* Check that PHY is ready */
while (!(readl(DSIPHY_PLL_RDY) & 0x01))
udelay(1);
writel(0x202D, DSI_CLKOUT_TIMING_CTRL);
off = 0x0440; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
writel(pd->timing[i], MIPI_DSI_BASE + off);
off += 4;
}
}
return 0;
}
int mipi_dsi_video_mode_config(unsigned short disp_width,
unsigned short disp_height,
unsigned short img_width,
unsigned short img_height,
unsigned short hsync_porch0_fp,
unsigned short hsync_porch0_bp,
unsigned short vsync_porch0_fp,
unsigned short vsync_porch0_bp,
unsigned short hsync_width,
unsigned short vsync_width,
unsigned short dst_format,
unsigned short traffic_mode,
unsigned char lane_en,
unsigned low_pwr_stop_mode,
unsigned char eof_bllp_pwr,
unsigned char interleav)
{
int status = 0;
/* disable mdp first */
mdp_disable();
writel(0x00000000, DSI_CLK_CTRL);
writel(0x00000000, DSI_CLK_CTRL);
writel(0x00000000, DSI_CLK_CTRL);
writel(0x00000000, DSI_CLK_CTRL);
writel(0x00000002, DSI_CLK_CTRL);
writel(0x00000006, DSI_CLK_CTRL);
writel(0x0000000e, DSI_CLK_CTRL);
writel(0x0000001e, DSI_CLK_CTRL);
writel(0x0000023f, DSI_CLK_CTRL);
writel(0, DSI_CTRL);
writel(0, DSI_ERR_INT_MASK0);
writel(0x02020202, DSI_INT_CTRL);
writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
DSI_VIDEO_MODE_ACTIVE_H);
writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
DSI_VIDEO_MODE_ACTIVE_V);
if (mdp_get_revision() >= MDP_REV_41) {
writel(((disp_height + vsync_porch0_fp
+ vsync_porch0_bp - 1) << 16)
| (disp_width + hsync_porch0_fp
+ hsync_porch0_bp - 1),
DSI_VIDEO_MODE_TOTAL);
} else {
writel(((disp_height + vsync_porch0_fp
+ vsync_porch0_bp) << 16)
| (disp_width + hsync_porch0_fp
+ hsync_porch0_bp),
DSI_VIDEO_MODE_TOTAL);
}
writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC);
writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
writel(0x0, DSI_EOT_PACKET_CTRL);
writel(0x00000100, DSI_MISR_VIDEO_CTRL);
if (mdp_get_revision() >= MDP_REV_41) {
writel(low_pwr_stop_mode << 16 |
eof_bllp_pwr << 12 | traffic_mode << 8
| dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
} else {
writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
eof_bllp_pwr << 12 | traffic_mode << 8
| dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
}
writel(0x3fd08, DSI_HS_TIMER_CTRL);
writel(0x67, DSI_CAL_STRENGTH_CTRL);
writel(0x80006711, DSI_CAL_CTRL);
writel(0x00010100, DSI_MISR_VIDEO_CTRL);
writel(0x00010100, DSI_INT_CTRL);
writel(0x02010202, DSI_INT_CTRL);
writel(0x02030303, DSI_INT_CTRL);
writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
| 0x103, DSI_CTRL);
return status;
}
int msm_display_config()
{
int ret = NO_ERROR;
struct msm_panel_info *pinfo;
if (!panel)
return ERR_INVALID_ARGS;
pinfo = &(panel->panel_info);
/* Set MDP revision */
mdp_set_revision(panel->mdp_rev);
switch (pinfo->type) {
case LVDS_PANEL:
dprintf(INFO, "Config LVDS_PANEL.\n");
ret = mdp_lcdc_config(pinfo, &(panel->fb));
if (ret)
goto msm_display_config_out;
break;
case MIPI_VIDEO_PANEL:
dprintf(INFO, "Config MIPI_VIDEO_PANEL.\n");
if (mdp_get_revision() == MDP_REV_50)
ret = mdss_dsi_config(panel);
else
ret = mipi_config(panel);
if (ret)
goto msm_display_config_out;
if (pinfo->early_config)
ret = pinfo->early_config((void *)pinfo);
ret = mdp_dsi_video_config(pinfo, &(panel->fb));
if (ret)
goto msm_display_config_out;
break;
case MIPI_CMD_PANEL:
dprintf(INFO, "Config MIPI_CMD_PANEL.\n");
ret = mipi_config(panel);
if (ret)
goto msm_display_config_out;
ret = mdp_dsi_cmd_config(pinfo, &(panel->fb));
if (ret)
goto msm_display_config_out;
break;
case LCDC_PANEL:
dprintf(INFO, "Config LCDC PANEL.\n");
ret = mdp_lcdc_config(pinfo, &(panel->fb));
if (ret)
goto msm_display_config_out;
break;
default:
return ERR_INVALID_ARGS;
};
if (pinfo->config)
ret = pinfo->config((void *)pinfo);
msm_display_config_out:
return ret;
}
