/* create the shared memory BAR when we are not using the server, so we can
* create the BAR and map the memory immediately */
static void create_shared_memory_BAR(IVShmemState *s, int fd) {
void * ptr;
s->shm_fd = fd;
ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
memory_region_init_ram_ptr(&s->ivshmem, &s->dev.qdev, "ivshmem.bar2",
s->ivshmem_size, ptr);
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* region for shared memory */
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
}
/* create the shared memory BAR when we are not using the server, so we can
* create the BAR and map the memory immediately */
static void create_shared_memory_BAR(IVShmemState *s, int fd) {
void * ptr;
s->shm_fd = fd;
ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2",
s->ivshmem_size, ptr);
vmstate_register_ram(&s->ivshmem, DEVICE(s));
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* region for shared memory */
pci_register_bar(PCI_DEVICE(s), 2, s->ivshmem_attr, &s->bar);
}
static void process_msg_shmem(IVShmemState *s, int fd, Error **errp)
{
struct stat buf;
size_t size;
void *ptr;
if (s->ivshmem_bar2) {
error_setg(errp, "server sent unexpected shared memory message");
close(fd);
return;
}
if (fstat(fd, &buf) < 0) {
error_setg_errno(errp, errno,
"can't determine size of shared memory sent by server");
close(fd);
return;
}
size = buf.st_size;
/* Legacy cruft */
if (s->legacy_size != SIZE_MAX) {
if (size < s->legacy_size) {
error_setg(errp, "server sent only %zd bytes of shared memory",
(size_t)buf.st_size);
close(fd);
return;
}
size = s->legacy_size;
}
/* mmap the region and map into the BAR2 */
ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
if (ptr == MAP_FAILED) {
error_setg_errno(errp, errno, "Failed to mmap shared memory");
close(fd);
return;
}
memory_region_init_ram_ptr(&s->server_bar2, OBJECT(s),
"ivshmem.bar2", size, ptr);
memory_region_set_fd(&s->server_bar2, fd);
s->ivshmem_bar2 = &s->server_bar2;
}
/* create the shared memory BAR when we are not using the server, so we can
* create the BAR and map the memory immediately */
static int create_shared_memory_BAR(IVShmemState *s, int fd, uint8_t attr,
Error **errp)
{
void * ptr;
ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
if (ptr == MAP_FAILED) {
error_setg_errno(errp, errno, "Failed to mmap shared memory");
return -1;
}
memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2",
s->ivshmem_size, ptr);
qemu_set_ram_fd(s->ivshmem.ram_addr, fd);
vmstate_register_ram(&s->ivshmem, DEVICE(s));
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* region for shared memory */
pci_register_bar(PCI_DEVICE(s), 2, attr, &s->bar);
return 0;
}
Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
unsigned long ram_size)
{
qemu_irq cpu_irq[EXYNOS4210_NCPUS];
int i, n;
Exynos4210State *s = g_new(Exynos4210State, 1);
qemu_irq *irqp;
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
unsigned long mem_size;
DeviceState *dev;
SysBusDevice *busdev;
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
s->cpu[n] = cpu_arm_init("cortex-a9");
if (!s->cpu[n]) {
fprintf(stderr, "Unable to find CPU %d definition\n", n);
exit(1);
}
/* Create PIC controller for each processor instance */
irqp = arm_pic_init_cpu(s->cpu[n]);
/*
* Get GICs gpio_in cpu_irq to connect a combiner to them later.
* Use only IRQ for a while.
*/
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
/*** IRQs ***/
s->irq_table = exynos4210_init_irq(&s->irqs);
/* IRQ Gate */
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
dev = qdev_create(NULL, "exynos4210.irq_gate");
qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
qdev_init_nofail(dev);
/* Get IRQ Gate input in gate_irq */
for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
gate_irq[i][n] = qdev_get_gpio_in(dev, n);
}
busdev = SYS_BUS_DEVICE(dev);
/* Connect IRQ Gate output to cpu_irq */
sysbus_connect_irq(busdev, 0, cpu_irq[i]);
}
/* Private memory region and Internal GIC */
dev = qdev_create(NULL, "a9mpcore_priv");
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n, gate_irq[n][0]);
}
for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
}
/* Cache controller */
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
/* External GIC */
dev = qdev_create(NULL, "exynos4210.gic");
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
/* Map CPU interface */
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
/* Map Distributer interface */
sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n, gate_irq[n][1]);
}
for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
}
/* Internal Interrupt Combiner */
dev = qdev_create(NULL, "exynos4210.combiner");
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
}
exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
/* External Interrupt Combiner */
dev = qdev_create(NULL, "exynos4210.combiner");
qdev_prop_set_uint32(dev, "external", 1);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
}
exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
/* Initialize board IRQs. */
exynos4210_init_board_irqs(&s->irqs);
/*** Memory ***/
/* Chip-ID and OMR */
memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
sizeof(chipid_and_omr), chipid_and_omr);
memory_region_set_readonly(&s->chipid_mem, true);
memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
&s->chipid_mem);
/* Internal ROM */
memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
EXYNOS4210_IROM_SIZE);
memory_region_set_readonly(&s->irom_mem, true);
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
&s->irom_mem);
/* mirror of iROM */
memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
&s->irom_mem,
0,
EXYNOS4210_IROM_SIZE);
memory_region_set_readonly(&s->irom_alias_mem, true);
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
&s->irom_alias_mem);
/* Internal RAM */
memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
EXYNOS4210_IRAM_SIZE);
vmstate_register_ram_global(&s->iram_mem);
memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
&s->iram_mem);
/* DRAM */
mem_size = ram_size;
if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
mem_size - EXYNOS4210_DRAM_MAX_SIZE);
vmstate_register_ram_global(&s->dram1_mem);
memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
&s->dram1_mem);
mem_size = EXYNOS4210_DRAM_MAX_SIZE;
}
memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
vmstate_register_ram_global(&s->dram0_mem);
memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
&s->dram0_mem);
/* PMU.
* The only reason of existence at the moment is that secondary CPU boot
* loader uses PMU INFORM5 register as a holding pen.
*/
sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
/* PWM */
sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
s->irq_table[exynos4210_get_irq(22, 0)],
s->irq_table[exynos4210_get_irq(22, 1)],
s->irq_table[exynos4210_get_irq(22, 2)],
s->irq_table[exynos4210_get_irq(22, 3)],
s->irq_table[exynos4210_get_irq(22, 4)],
NULL);
/* RTC */
sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
s->irq_table[exynos4210_get_irq(23, 0)],
s->irq_table[exynos4210_get_irq(23, 1)],
NULL);
/* Multi Core Timer */
dev = qdev_create(NULL, "exynos4210.mct");
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
for (n = 0; n < 4; n++) {
/* Connect global timer interrupts to Combiner gpio_in */
sysbus_connect_irq(busdev, n,
s->irq_table[exynos4210_get_irq(1, 4 + n)]);
}
/* Connect local timer interrupts to Combiner gpio_in */
sysbus_connect_irq(busdev, 4,
s->irq_table[exynos4210_get_irq(51, 0)]);
sysbus_connect_irq(busdev, 5,
s->irq_table[exynos4210_get_irq(35, 3)]);
sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
/*** I2C ***/
for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
qemu_irq i2c_irq;
if (n < 8) {
i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
} else {
i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
}
dev = qdev_create(NULL, "exynos4210.i2c");
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(busdev, 0, i2c_irq);
sysbus_mmio_map(busdev, 0, addr);
s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
}
/*** UARTs ***/
exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
/*** Display controller (FIMD) ***/
sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
s->irq_table[exynos4210_get_irq(11, 0)],
s->irq_table[exynos4210_get_irq(11, 1)],
s->irq_table[exynos4210_get_irq(11, 2)],
NULL);
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
s->irq_table[exynos4210_get_irq(28, 3)]);
return s;
}
static void ivshmem_read(void *opaque, const uint8_t * buf, int flags)
{
IVShmemState *s = opaque;
int incoming_fd, tmp_fd;
int guest_max_eventfd;
long incoming_posn;
memcpy(&incoming_posn, buf, sizeof(long));
/* pick off s->server_chr->msgfd and store it, posn should accompany msg */
tmp_fd = qemu_chr_fe_get_msgfd(s->server_chr);
IVSHMEM_DPRINTF("posn is %ld, fd is %d\n", incoming_posn, tmp_fd);
/* make sure we have enough space for this guest */
if (incoming_posn >= s->nb_peers) {
increase_dynamic_storage(s, incoming_posn);
}
if (tmp_fd == -1) {
/* if posn is positive and unseen before then this is our posn*/
if ((incoming_posn >= 0) &&
(s->peers[incoming_posn].eventfds == NULL)) {
/* receive our posn */
s->vm_id = incoming_posn;
return;
} else {
/* otherwise an fd == -1 means an existing guest has gone away */
IVSHMEM_DPRINTF("posn %ld has gone away\n", incoming_posn);
close_guest_eventfds(s, incoming_posn);
return;
}
}
/* because of the implementation of get_msgfd, we need a dup */
incoming_fd = dup(tmp_fd);
if (incoming_fd == -1) {
fprintf(stderr, "could not allocate file descriptor %s\n",
strerror(errno));
return;
}
/* if the position is -1, then it's shared memory region fd */
if (incoming_posn == -1) {
void * map_ptr;
s->max_peer = 0;
if (check_shm_size(s, incoming_fd) == -1) {
exit(-1);
}
/* mmap the region and map into the BAR2 */
map_ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED,
incoming_fd, 0);
memory_region_init_ram_ptr(&s->ivshmem,
"ivshmem.bar2", s->ivshmem_size, map_ptr);
vmstate_register_ram(&s->ivshmem, &s->dev.qdev);
IVSHMEM_DPRINTF("guest h/w addr = %" PRIu64 ", size = %" PRIu64 "\n",
s->ivshmem_offset, s->ivshmem_size);
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* only store the fd if it is successfully mapped */
s->shm_fd = incoming_fd;
return;
}
/* each guest has an array of eventfds, and we keep track of how many
* guests for each VM */
guest_max_eventfd = s->peers[incoming_posn].nb_eventfds;
if (guest_max_eventfd == 0) {
/* one eventfd per MSI vector */
s->peers[incoming_posn].eventfds = g_new(EventNotifier, s->vectors);
}
/* this is an eventfd for a particular guest VM */
IVSHMEM_DPRINTF("eventfds[%ld][%d] = %d\n", incoming_posn,
guest_max_eventfd, incoming_fd);
event_notifier_init_fd(&s->peers[incoming_posn].eventfds[guest_max_eventfd],
incoming_fd);
/* increment count for particular guest */
s->peers[incoming_posn].nb_eventfds++;
/* keep track of the maximum VM ID */
if (incoming_posn > s->max_peer) {
s->max_peer = incoming_posn;
}
if (incoming_posn == s->vm_id) {
s->eventfd_chr[guest_max_eventfd] = create_eventfd_chr_device(s,
&s->peers[s->vm_id].eventfds[guest_max_eventfd],
guest_max_eventfd);
}
if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
ivshmem_add_eventfd(s, incoming_posn, guest_max_eventfd);
}
}
/* create the shared memory BAR when we are not using the server, so we can
* create the BAR and map the memory immediately */
static int create_shared_memory_BAR(IVShmemState *s,
IVShmemFile f[IVSHMEM_MAX_FILES], int num_files) {
void * ptr_data, * virt_area;
uint64_t total_size = 0, one_gb_align;
int i, fd_zero;
/* open /dev/zero for mmap */
fd_zero = open("/dev/zero", O_RDWR);
if (fd_zero < 0) {
fprintf(stderr, "ivshmem: opening /dev/zero failed (%s)\n",
strerror(errno));
return -1;
}
/* Get virtual area of ivshmem_size plus 1GB for alignment.
* virt_area later will be used to remap files backed up by hugepages (1GB
* or 2MB). Therefore and due to mmap restrictions virt_area will have to
* be aligned to both 1GB and 2MB (1GB will cover both scenarios). In order
* to be sure we can freely align virt_area up to 1GB we reserve vshmem_size
* plus 1GB */
virt_area = mmap(NULL, s->ivshmem_size + ONE_GB,
PROT_READ|PROT_WRITE,
MAP_PRIVATE, fd_zero, 0);
if (virt_area == MAP_FAILED) {
fprintf(stderr, "ivshmem: mmap /dev/zero failed (%s)\n",
strerror(errno));
return -1;
}
/* Calculate 1GB boundary alignment covering 1GB and 2MB hugepage cases */
one_gb_align = ONE_GB - ((uint64_t) virt_area % ONE_GB);
munmap(virt_area, s->ivshmem_size + ONE_GB);
close(fd_zero);
/* Finally align virt_area to 1GB boundary. */
virt_area += one_gb_align;
/* at this point virt_area contains a virtual address that where we can
* safely use to mmap all ivshmem files.
* Proceed to mmap all ivshmem files so. */
for (i = 0; i < num_files; i++) {
/* remap file into the start of virtual area */
ptr_data = mmap(virt_area + total_size,
f[i].size, PROT_READ|PROT_WRITE,
MAP_SHARED | MAP_FIXED, f[i].fd, f[i].offset);
/* we need to make sure we get _exactly_ what we want */
if (ptr_data == MAP_FAILED || ptr_data != virt_area + total_size) {
fprintf(stderr, "ivshmem: mmap failed (%s)\n", strerror(errno));
return -1;
}
total_size += f[i].size;
}
memcpy(s->shm_fds, f, sizeof(s->shm_fds));
memory_region_init_ram_ptr(&s->ivshmem, "ivshmem.bar2",
s->ivshmem_size, virt_area);
vmstate_register_ram(&s->ivshmem, &s->dev.qdev);
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* region for shared memory */
pci_register_bar(&s->dev, 2, s->ivshmem_attr, &s->bar);
return 0;
}
static void ivshmem_read(void *opaque, const uint8_t *buf, int size)
{
IVShmemState *s = opaque;
int incoming_fd;
int new_eventfd;
int64_t incoming_posn;
Error *err = NULL;
Peer *peer;
if (!fifo_update_and_get_i64(s, buf, size, &incoming_posn)) {
return;
}
if (incoming_posn < -1) {
IVSHMEM_DPRINTF("invalid incoming_posn %" PRId64 "\n", incoming_posn);
return;
}
/* pick off s->server_chr->msgfd and store it, posn should accompany msg */
incoming_fd = qemu_chr_fe_get_msgfd(s->server_chr);
IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n",
incoming_posn, incoming_fd);
/* make sure we have enough space for this peer */
if (incoming_posn >= s->nb_peers) {
if (resize_peers(s, incoming_posn + 1) < 0) {
error_report("failed to resize peers array");
if (incoming_fd != -1) {
close(incoming_fd);
}
return;
}
}
peer = &s->peers[incoming_posn];
if (incoming_fd == -1) {
/* if posn is positive and unseen before then this is our posn*/
if (incoming_posn >= 0 && s->vm_id == -1) {
/* receive our posn */
s->vm_id = incoming_posn;
} else {
/* otherwise an fd == -1 means an existing peer has gone away */
IVSHMEM_DPRINTF("posn %" PRId64 " has gone away\n", incoming_posn);
close_peer_eventfds(s, incoming_posn);
}
return;
}
/* if the position is -1, then it's shared memory region fd */
if (incoming_posn == -1) {
void * map_ptr;
if (memory_region_is_mapped(&s->ivshmem)) {
error_report("shm already initialized");
close(incoming_fd);
return;
}
if (check_shm_size(s, incoming_fd, &err) == -1) {
error_report_err(err);
close(incoming_fd);
return;
}
/* mmap the region and map into the BAR2 */
map_ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED,
incoming_fd, 0);
if (map_ptr == MAP_FAILED) {
error_report("Failed to mmap shared memory %s", strerror(errno));
close(incoming_fd);
return;
}
memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s),
"ivshmem.bar2", s->ivshmem_size, map_ptr);
qemu_set_ram_fd(s->ivshmem.ram_addr, incoming_fd);
vmstate_register_ram(&s->ivshmem, DEVICE(s));
IVSHMEM_DPRINTF("guest h/w addr = %p, size = %" PRIu64 "\n",
map_ptr, s->ivshmem_size);
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
return;
}
/* each peer has an associated array of eventfds, and we keep
* track of how many eventfds received so far */
/* get a new eventfd: */
if (peer->nb_eventfds >= s->vectors) {
error_report("Too many eventfd received, device has %d vectors",
s->vectors);
close(incoming_fd);
return;
}
new_eventfd = peer->nb_eventfds++;
/* this is an eventfd for a particular peer VM */
IVSHMEM_DPRINTF("eventfds[%" PRId64 "][%d] = %d\n", incoming_posn,
new_eventfd, incoming_fd);
event_notifier_init_fd(&peer->eventfds[new_eventfd], incoming_fd);
fcntl_setfl(incoming_fd, O_NONBLOCK); /* msix/irqfd poll non block */
if (incoming_posn == s->vm_id) {
setup_interrupt(s, new_eventfd);
}
if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
ivshmem_add_eventfd(s, incoming_posn, new_eventfd);
}
}
