Exemplo n.º 1
0
int mhl_msc_recv_set_int(struct mhl_tx_ctrl *mhl_ctrl,
			 u8 offset, u8 set_int)
{
	int prior;
	if (offset >= 2)
		return -EFAULT;

	switch (offset) {
	case 0:
		if (set_int & MHL_INT_DCAP_CHG) {
			/* peer dcap has changed */
			mhl_ctrl->devcap_state = 0;
			mhl_msc_read_devcap_all(mhl_ctrl);
		}
		if (set_int & MHL_INT_DSCR_CHG) {
			/* peer's scratchpad reg changed */
			pr_debug("%s: dscr chg\n", __func__);
			mhl_read_scratchpad(mhl_ctrl);
			mhl_ctrl->scrpd_busy = false;
		}
		if (set_int & MHL_INT_REQ_WRT) {
			/* SET_INT: REQ_WRT */
			if (mhl_ctrl->scrpd_busy) {
				prior = MSC_NORMAL_SEND;
			} else {
				prior = MSC_PRIORITY_SEND;
				mhl_ctrl->scrpd_busy = true;
			}
			mhl_msc_send_set_int(
				mhl_ctrl,
				MHL_RCHANGE_INT,
				MHL_INT_GRT_WRT,
				prior);
		}
		if (set_int & MHL_INT_GRT_WRT) {
			/* SET_INT: GRT_WRT */
			pr_debug("%s: recvd req to permit/grant write",
				 __func__);
			complete_all(&mhl_ctrl->req_write_done);
			mhl_msc_write_burst(
				mhl_ctrl,
				MHL_SCRATCHPAD_OFFSET,
				mhl_ctrl->scrpd.data,
				mhl_ctrl->scrpd.length);
		}
		break;
	case 1:
		if (set_int & MHL_INT_EDID_CHG) {
			/* peer EDID has changed
			 * toggle HPD to read EDID
			 */
			pr_debug("%s: EDID CHG\n", __func__);
			mhl_drive_hpd(mhl_ctrl, HPD_DOWN);
			msleep(110);
			mhl_drive_hpd(mhl_ctrl, HPD_UP);
		}
	}
	return 0;
}
static int mhl_msc_recv_write_stat(u8 offset, u8 value)
{
	if (offset >= 2)
		return -EFAULT;

	switch (offset) {
	case 0:
		
		pr_debug("MHL: value [0x%02x]\n", value);
		pr_debug("MHL: offset [0x%02x]\n", offset);
		pr_debug("MHL: devcap state [0x%02x]\n",
			mhl_msm_state->devcap_state);
		pr_debug("MHL: MHL_STATUS_DCAP_RDY [0x%02x]\n",
			MHL_STATUS_DCAP_RDY);
		if (((value ^ mhl_msm_state->devcap_state) &
			MHL_STATUS_DCAP_RDY)) {
			if (value & MHL_STATUS_DCAP_RDY) {
				if (mhl_msc_read_devcap_all() == -EBUSY) {
					pr_err("READ DEVCAP FAILED to send successfully\n");
					break;
				}
			} else {
				
			}
		}
		break;
	case 1:
		
		if ((value ^ mhl_msm_state->path_en_state)
			& MHL_STATUS_PATH_ENABLED) {
			if (value & MHL_STATUS_PATH_ENABLED) {
				mhl_msm_state->path_en_state
					|= (MHL_STATUS_PATH_ENABLED |
					MHL_STATUS_CLK_MODE_NORMAL);
				mhl_msc_send_write_stat(
					MHL_STATUS_REG_LINK_MODE,
					mhl_msm_state->path_en_state);
			} else {
				mhl_msm_state->path_en_state
					&= ~(MHL_STATUS_PATH_ENABLED |
					MHL_STATUS_CLK_MODE_NORMAL);
				mhl_msc_send_write_stat(
					MHL_STATUS_REG_LINK_MODE,
					mhl_msm_state->path_en_state);
			}
		}
		break;
	}
	mhl_msm_state->path_en_state = value;
	return 0;
}
Exemplo n.º 3
0
static int mhl_msc_recv_set_int(u8 offset, u8 set_int)
{
	if (offset >= 2)
		return -EFAULT;

	switch (offset) {
	case 0:
		/* DCAP_CHG */
		if (set_int & MHL_INT_DCAP_CHG) {
			/* peer dcap has changed */
			if (mhl_msc_read_devcap_all() == -EBUSY) {
				pr_err("READ DEVCAP FAILED to send successfully\n");
				break;
			}
		}
		/* DSCR_CHG */
		if (set_int & MHL_INT_DSCR_CHG)
			;
		/* REQ_WRT */
		if (set_int & MHL_INT_REQ_WRT) {
			/* SET_INT: GRT_WRT */
			mhl_msc_send_set_int(
				MHL_RCHANGE_INT,
				MHL_INT_GRT_WRT);
		}
		/* GRT_WRT */
		if (set_int & MHL_INT_GRT_WRT)
			;
		break;
	case 1:
		/* EDID_CHG */
		if (set_int & MHL_INT_EDID_CHG) {
			/* peer EDID has changed.
			 * toggle HPD to read EDID again
			 * In 8x30 FLUID  HDMI HPD line
			 * is not connected
			 * with MHL 8334 transmitter
			 */
		}
	}
	return 0;
}
static int mhl_msc_recv_set_int(u8 offset, u8 set_int)
{
	if (offset >= 2)
		return -EFAULT;

	switch (offset) {
	case 0:
		
		if (set_int & MHL_INT_DCAP_CHG) {
			
			if (mhl_msc_read_devcap_all() == -EBUSY) {
				pr_err("READ DEVCAP FAILED to send successfully\n");
				break;
			}
		}
		
		if (set_int & MHL_INT_DSCR_CHG)
			;
		
		if (set_int & MHL_INT_REQ_WRT) {
			
			mhl_msc_send_set_int(
				MHL_RCHANGE_INT,
				MHL_INT_GRT_WRT);
		}
		
		if (set_int & MHL_INT_GRT_WRT)
			;
		break;
	case 1:
		
		if (set_int & MHL_INT_EDID_CHG) {
		}
	}
	return 0;
}
Exemplo n.º 5
0
int mhl_msc_recv_write_stat(struct mhl_tx_ctrl *mhl_ctrl,
			    u8 offset, u8 value)
{
	bool tmds_en;

	if (offset >= 2)
		return -EFAULT;

	switch (offset) {
	case 0:
		/*
		 * connected device bits
		 * changed and DEVCAP READY
		 */
		if (((value ^ mhl_ctrl->status[offset]) &
		     MHL_STATUS_DCAP_RDY)) {
			if (value & MHL_STATUS_DCAP_RDY) {
				mhl_ctrl->devcap_state = 0;
				mhl_msc_read_devcap_all(mhl_ctrl);
			} else {
				/*
				 * peer dcap turned not ready
				 * use old devap state
				 */
				pr_debug("%s: DCAP RDY bit cleared\n",
					 __func__);
			}
		}
		break;
	case 1:
		/*
		 * connected device bits
		 * changed and PATH ENABLED
		 * bit set
		 */
		tmds_en = mhl_check_tmds_enabled(mhl_ctrl);
		if ((value ^ mhl_ctrl->status[offset])
		    & MHL_STATUS_PATH_ENABLED) {
			if (value & MHL_STATUS_PATH_ENABLED) {
				if (tmds_en &&
				    (mhl_ctrl->devcap[offset] &
				     MHL_FEATURE_RAP_SUPPORT)) {
					mhl_msc_send_msc_msg(
						mhl_ctrl,
						MHL_MSC_MSG_RAP,
						MHL_RAP_CONTENT_ON);
				}
				mhl_ctrl->path_en_state
					|= (MHL_STATUS_PATH_ENABLED |
					    MHL_STATUS_CLK_MODE_NORMAL);
				mhl_msc_send_write_stat(
					mhl_ctrl,
					MHL_STATUS_REG_LINK_MODE,
					mhl_ctrl->path_en_state);
			} else {
				mhl_ctrl->path_en_state
					&= ~(MHL_STATUS_PATH_ENABLED |
					     MHL_STATUS_CLK_MODE_NORMAL);
				mhl_msc_send_write_stat(
					mhl_ctrl,
					MHL_STATUS_REG_LINK_MODE,
					mhl_ctrl->path_en_state);
			}
		}
		break;
	}
	mhl_ctrl->status[offset] = value;
	return 0;
}