static int
miiphyinit(Mii *mii)
{
ulong dev;
Ctlr *ctlr;
Gbereg *reg;
ctlr = (Ctlr*)mii->ctlr;
reg = ctlr->reg;
dev = reg->phy;
MIIDBG("phy dev addr %lux\n", dev);
/* leds link & activity */
miiregpage(mii, dev, Pagled);
/* low 4 bits == 1: on - link, blink - activity, off - no link */
miiwr(mii, dev, Scr, (miird(mii, dev, Scr) & ~0xf) | 1);
miiregpage(mii, dev, Pagrgmii);
miiwr(mii, dev, Scr, miird(mii, dev, Scr) | Rgmiipwrup);
/* must now do a software reset, says the manual */
miireset(ctlr->mii);
/* enable RGMII delay on Tx and Rx for CPU port */
miiwr(mii, dev, Recr, miird(mii, dev, Recr) | Rxtiming | Rxtiming);
/* must now do a software reset, says the manual */
miireset(ctlr->mii);
miiregpage(mii, dev, Pagcopper);
miiwr(mii, dev, Scr,
(miird(mii, dev, Scr) & ~(Pwrdown|Endetect)) | Mdix);
return 0;
}
static void
phyinit(Dev *d)
{
int i;
miiwr(d, Bmcr, Bmcrreset|Anenable);
for(i = 0; i < Resettime/10; i++){
if((miird(d, Bmcr) & Bmcrreset) == 0)
break;
sleep(10);
}
miiwr(d, Advertise, Adcsma|Adall|Adpause|Adpauseasym);
// miiwr(d, Advertise, Adcsma|Ad10f|Ad10h|Adpause|Adpauseasym);
miird(d, Phyintsrc);
miiwr(d, Phyintmask, Anegcomp|Linkdown);
miiwr(d, Bmcr, miird(d, Bmcr)|Anenable|Anrestart);
}
static void
miiregpage(Mii *mii, ulong dev, ulong page)
{
miiwr(mii, dev, Eadr, page);
}
