void mdp4_dsi_cmd_vsync_ctrl(int cndx, int enable)
{
struct vsycn_ctrl *vctrl;
if (cndx >= MAX_CONTROLLER) {
pr_err("%s: out or range: cndx=%d\n", __func__, cndx);
return;
}
vctrl = &vsync_ctrl_db[cndx];
if (vctrl->vsync_irq_enabled == enable)
return;
vctrl->vsync_irq_enabled = enable;
mutex_lock(&vctrl->update_lock);
if (enable) {
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
} else {
mipi_dsi_clk_cfg(0);
mdp_clk_ctrl(0);
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
vctrl->expire_tick = 0;
}
mutex_unlock(&vctrl->update_lock);
}
static void clk_ctrl_work(struct work_struct *work)
{
unsigned long flags;
struct vsycn_ctrl *vctrl =
container_of(work, typeof(*vctrl), clk_work);
mutex_lock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->clk_control && vctrl->clk_enabled) {
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
vctrl->clk_enabled = 0;
vctrl->clk_control = 0;
#if 1 //Scott
complete_all(&vctrl->vsync_comp);
#endif
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
/* make sure dsi link is idle */
mipi_dsi_mdp_busy_wait();
mipi_dsi_clk_cfg(0);
mdp_clk_ctrl(0);
pr_debug("%s: SET_CLK_OFF, pid=%d\n", __func__, current->pid);
} else
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mutex_unlock(&vctrl->update_lock);
}
static int mdp4_dsi_cmd_clk_check(struct vsycn_ctrl *vctrl)
{
int clk_set_on = 0;
unsigned long flags;
mutex_lock(&vctrl->update_lock);
if (atomic_read(&vctrl->suspend)) {
mutex_unlock(&vctrl->update_lock);
pr_err("%s: suspended, no more pan display\n", __func__);
return -EPERM;
}
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
mutex_unlock(&vctrl->update_lock);
return 0;
}
static void clk_ctrl_work(struct work_struct *work)
{
unsigned long flags;
struct vsycn_ctrl *vctrl =
container_of(work, typeof(*vctrl), clk_work);
#if defined(PANTECH_LCD_WFD_CONNECTION_FAIL_ON_CMDMODE)
//shkwak 20130114, when using wfd, make clk_ctrl_work() does not control clk, for temporary
if(get_wfd_info())
return;
#endif
mutex_lock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->clk_control && vctrl->clk_enabled) {
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
vctrl->clk_enabled = 0;
vctrl->clk_control = 0;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
/* make sure dsi link is idle */
mipi_dsi_mdp_busy_wait();
mipi_dsi_clk_cfg(0);
mdp_clk_ctrl(0);
pr_debug("%s: SET_CLK_OFF, pid=%d\n", __func__, current->pid);
} else {
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
}
mutex_unlock(&vctrl->update_lock);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int clk_set_on = 0;
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mutex_lock(&vctrl->update_lock);
if (atomic_read(&vctrl->suspend)) {
mutex_unlock(&vctrl->update_lock);
pr_err("%s: suspended, no more pan display\n", __func__);
return;
}
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
mutex_unlock(&vctrl->update_lock);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mutex_lock(&mfd->dma->ov_mutex);
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_dsi_cmd_vsync_ctrl(struct fb_info *info, int enable)
{
#ifdef CONFIG_HUAWEI_KERNEL
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *) info->par;
static int old_imgType = -1;
#endif
struct vsycn_ctrl *vctrl;
unsigned long flags;
int cndx = 0;
int clk_set_on = 0;
vctrl = &vsync_ctrl_db[cndx];
mutex_lock(&vctrl->update_lock);
pr_debug("%s: clk_enabled=%d vsync_enabled=%d req=%d\n", __func__,
vctrl->clk_enabled, vctrl->vsync_enabled, enable);
if (vctrl->vsync_enabled == enable) {
mutex_unlock(&vctrl->update_lock);
return;
}
vctrl->vsync_enabled = enable;
if (enable) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->expire_tick = 0;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (vctrl->clk_enabled == 0) {
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vctrl->clk_enabled = 1;
vctrl->new_update = 1;
clk_set_on = 1;
}
if (clk_set_on) {
vsync_irq_enable(INTR_PRIMARY_RDPTR,
MDP_PRIM_RDPTR_TERM);
}
/*baseline 1.5 to 1.7 be deleted,we believe it's Qual's bug*/
#ifdef CONFIG_HUAWEI_KERNEL
if( mfd->fb_imgType != old_imgType)
{
old_imgType = mfd->fb_imgType;
mdp4_overlay_update_dsi_cmd(mfd);
}
#endif
} else {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
}
mutex_unlock(&vctrl->update_lock);
}
void mdp4_dsi_cmd_vsync_ctrl(struct fb_info *info, int enable)
{
struct vsycn_ctrl *vctrl;
unsigned long flags;
int cndx = 0;
int clk_set_on = 0;
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: clk_enabled=%d vsycn_enabeld=%d req=%d\n", __func__,
vctrl->clk_enabled, vctrl->vsync_enabled, enable);
mutex_lock(&vctrl->update_lock);
if (vctrl->vsync_enabled == enable) {
mutex_unlock(&vctrl->update_lock);
return;
}
vctrl->vsync_enabled = enable;
if (enable) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->expire_tick = 0;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (vctrl->clk_enabled == 0) {
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vctrl->clk_enabled = 1;
clk_set_on = 1;
}
if (clk_set_on) {
vsync_irq_enable(INTR_PRIMARY_RDPTR,
MDP_PRIM_RDPTR_TERM);
}
} else {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
}
mutex_unlock(&vctrl->update_lock);
#ifdef CLOCK_CONTROL
mutex_lock(&vctrl->update_lock);
if (enable) {
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
} else {
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
mutex_unlock(&vctrl->update_lock);
#endif
}
static int set_sre(int level)
{
int ret = 0;
pr_info("%s sre level = %d\n",__func__,level);
mipi_dsi_clk_cfg(1);
mipi_set_tx_power_mode(0);
switch(level)
{
case 0:
mipi_dsi_cmds_tx(&orise_tx_buf, sre_off_sequence,
ARRAY_SIZE(sre_off_sequence));
break;
break;
case 1:
mipi_dsi_cmds_tx(&orise_tx_buf, sre_weak_mode_sequence,
ARRAY_SIZE(sre_weak_mode_sequence));
break;
case 2:
mipi_dsi_cmds_tx(&orise_tx_buf, sre_middle_mode_sequence,
ARRAY_SIZE(sre_middle_mode_sequence));
break;
case 3:
mipi_dsi_cmds_tx(&orise_tx_buf, sre_strong_mode_sequence,
ARRAY_SIZE(sre_strong_mode_sequence));
break;
case 4:
mipi_dsi_cmds_tx(&orise_tx_buf, sre_manual_mode_sequence,
ARRAY_SIZE(sre_manual_mode_sequence));
default:
pr_err("%s Level %d is not supported!\n",__func__,level);
ret = -1;
break;
}
mipi_dsi_clk_cfg(0);
mipi_set_tx_power_mode(1);
return ret;
}
static int set_cabc(int level)
{
int ret = 0;
struct msm_fb_data_type *mfd;
pr_info("%s Neal level = %d\n",__func__,level);
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mipi_dsi_clk_cfg(1);
mipi_set_tx_power_mode(0);
//mutex_lock(&mfd->dma->ov_mutex);
switch(level)
{
case 0:
mipi_dsi_cmds_tx(&orise_tx_buf, cabc_off_sequence,
ARRAY_SIZE(cabc_off_sequence));
break;
case 1:
mipi_dsi_cmds_tx(&orise_tx_buf, cabc_user_interface_image_sequence,
ARRAY_SIZE(cabc_user_interface_image_sequence));
break;
case 2:
mipi_dsi_cmds_tx(&orise_tx_buf, cabc_still_image_sequence,
ARRAY_SIZE(cabc_still_image_sequence));
break;
case 3:
mipi_dsi_cmds_tx(&orise_tx_buf, cabc_video_image_sequence,
ARRAY_SIZE(cabc_video_image_sequence));
break;
default:
pr_err("%s Leavel %d is not supported!\n",__func__,level);
ret = -1;
break;
}
//mutex_unlock(&mfd->dma->ov_mutex);
mipi_set_tx_power_mode(1);
mipi_dsi_clk_cfg(0);
return ret;
}
void mdp4_dsi_cmd_vsync_ctrl(struct fb_info *info, int enable)
{
struct vsycn_ctrl *vctrl;
unsigned long flags;
int clk_set_on = 0;
int cndx = 0;
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: clk_enabled=%d vsync_enabled=%d req=%d suspend=%d\n",
__func__, vctrl->clk_enabled, vctrl->vsync_enabled, enable,
atomic_read(&vctrl->suspend));
if (atomic_read(&vctrl->suspend)) {
if (vctrl->vsync_enabled)
pr_warning("[DISP] %s: suspended, no more vsync event ctrl\n", __func__);
enable = 0;
}
mutex_lock(&vctrl->update_lock);
if (vctrl->vsync_enabled == enable) {
mutex_unlock(&vctrl->update_lock);
return;
}
vctrl->vsync_enabled = enable;
if (enable) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->expire_tick = 0;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (vctrl->clk_enabled == 0) {
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1, 0);
mdp_clk_ctrl(1);
vctrl->clk_enabled = 1;
clk_set_on = 1;
}
if (clk_set_on) {
vsync_irq_enable(INTR_PRIMARY_RDPTR,
MDP_PRIM_RDPTR_TERM);
}
} else {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
}
mutex_unlock(&vctrl->update_lock);
}
static void clk_ctrl_work(struct work_struct *work)
{
struct vsycn_ctrl *vctrl =
container_of(work, typeof(*vctrl), clk_work);
unsigned long flags;
mutex_lock(&vctrl->update_lock);
if (vctrl->clk_control && vctrl->clk_enabled) {
pr_debug("%s: SET_CLK_OFF\n", __func__);
mdp_clk_ctrl(0);
mipi_dsi_clk_cfg(0);
spin_lock_irqsave(&vctrl->spin_lock, flags);
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
vctrl->clk_enabled = 0;
vctrl->clk_control = 0;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
}
mutex_unlock(&vctrl->update_lock);
}
/*
* mdp4_dsi_cmd_do_update:
* called from thread context
*/
void mdp4_dsi_cmd_pipe_queue(int cndx, struct mdp4_overlay_pipe *pipe)
{
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pp;
int undx;
if (cndx >= MAX_CONTROLLER) {
pr_err("%s: out or range: cndx=%d\n", __func__, cndx);
return;
}
vctrl = &vsync_ctrl_db[cndx];
if (atomic_read(&vctrl->suspend) > 0)
return;
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pp = &vp->plist[pipe->pipe_ndx - 1]; /* ndx start form 1 */
pr_debug("%s: vndx=%d pipe_ndx=%d expire=%x pid=%d\n", __func__,
undx, pipe->pipe_ndx, vctrl->expire_tick, current->pid);
*pp = *pipe; /* keep it */
vp->update_cnt++;
if (vctrl->expire_tick == 0) {
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
mutex_unlock(&vctrl->update_lock);
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
htc_mdp_sem_down(current, &mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
mipi_dsi_clk_cfg(1);
mipi_dsi_cmd_mdp_busy();
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
if (panel_type != PANEL_ID_PROTOU_LG && panel_type != PANEL_ID_PROTODCG_LG)
ret = panel_next_off(pdev);
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
htc_mdp_sem_up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
int disp_ext_blc_mode_select( uint8_t mode )
{
#ifdef DISP_BLC_CTRL_ENABLE
struct msm_fb_data_type *mfd;
DISP_LOCAL_LOG_EMERG("DISP mipi_novatek_wxga_cabc_mode_select mode=%d S\n",mode);
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_mipitx_lock();
disp_ext_util_disp_local_lock();
#endif /* CONFIG_DISP_EXT_UTIL */
if( disp_ext_util_get_disp_state() != LOCAL_DISPLAY_ON ) {
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
pr_err("%s:panel off\n", __func__);
return -1;
}
if( mode > 0x01 ) {
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
pr_err("%s:parameter err\n", __func__);
return -1;
}
if( select_mode_ctrl == mode ) {
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
DISP_LOCAL_LOG_EMERG("%s:Request a double. state=%d,req=%d\n",__func__,select_mode_ctrl,mode);
return 0;
}
mfd = mipi_novatek_wxga_get_mfd();
if( mfd == NULL ) {
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
pr_err("%s:mfd == NULL\n", __func__);
return -1;
}
select_mode_ctrl=mode;
msm_fb_pan_lock();
msm_fb_ioctl_ppp_lock();
msm_fb_ioctl_lut_lock();
mipi_dsi_mdp_busy_wait();
if( mode == 0 ) {
cabc_change[1] = 0;
}
else {
cabc_change[1] = select_mode;
}
pr_debug("%s:cabc_change[%d,%d]\n", __func__,cabc_change[0],cabc_change[1]);
DISP_LOCAL_LOG_EMERG("%s:cabc_change[%d,%d]\n", __func__,cabc_change[0],cabc_change[1]);
mipi_dsi_clk_cfg(1);
mipi_dsi_cmds_tx( &disp_ext_blc_tx_buf,
cabc_mode_select_cmds,
ARRAY_SIZE(cabc_mode_select_cmds));
mipi_dsi_clk_cfg(0);
udelay(1);
msm_fb_ioctl_lut_unlock();
msm_fb_ioctl_ppp_unlock();
msm_fb_pan_unlock();
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
pr_debug("%s:cabc select\n", __func__);
DISP_LOCAL_LOG_EMERG("DISP mipi_novatek_wxga_cabc_mode_select E\n");
#endif /*DISP_BLC_CTRL_ENABLE*/
return 0;
}
int mdp4_dsi_cmd_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
int undx;
int need_wait, cnt;
unsigned long flags;
pr_debug("%s+: pid=%d\n", __func__, current->pid);
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return ret;
}
need_wait = 0;
mutex_lock(&vctrl->update_lock);
atomic_set(&vctrl->suspend, 1);
complete_all(&vctrl->vsync_comp);
pr_debug("%s: clk=%d pan=%d\n", __func__,
vctrl->clk_enabled, vctrl->pan_display);
if (vctrl->clk_enabled)
need_wait = 1;
mutex_unlock(&vctrl->update_lock);
cnt = 0;
if (need_wait) {
while (vctrl->clk_enabled) {
msleep(20);
cnt++;
if (cnt > 10)
break;
}
}
if (cnt > 10) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->clk_enabled = 0;
vctrl->expire_tick = 0;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mipi_dsi_clk_cfg(0);
mdp_clk_ctrl(0);
pr_err("%s: Error, SET_CLK_OFF by force\n", __func__);
}
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
if (vctrl->vsync_enabled) {
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
vctrl->vsync_enabled = 0;
}
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
vp->update_cnt = 0; /* empty queue */
}
pr_debug("%s-:\n", __func__);
return ret;
}
int mdp4_dsi_cmd_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int need_dmap_wait = 0;
int need_ov_wait = 0;
int cnt = 0;
int clk_set_on = 0;
vctrl = &vsync_ctrl_db[0];
#ifdef FACTORY_TEST
if (!is_lcd_connected)
return 0;
#endif
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&vctrl->update_lock);
return 0;
}
mixer = pipe->mixer_num;
/*
* allow stage_commit without pipes queued
* (vp->update_cnt == 0) to unstage pipes after
* overlay_unset
*/
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
if(wait == 1) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
}
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_err("%s: warning, clock off while pan display\n", __func__);
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
}
if (mdp4_dsi_cmd_clk_check(vctrl) < 0)
return 0;
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
/* Blt */
if (vctrl->blt_wait)
need_dmap_wait = 1;
else if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
} else {
/* direct out */
if (vctrl->dmap_koff != vctrl->dmap_done) {
INIT_COMPLETION(vctrl->dmap_comp);
pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d\n",
__func__, vctrl->ov_koff, vctrl->ov_done,
vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());
need_dmap_wait = 1;
}
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_dmap_wait) {
pr_debug("%s: wait4dmap\n", __func__);
mdp4_dsi_cmd_wait4dmap(0);
}
#if defined(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_WVGA_PT) \
|| defined(CONFIG_FB_MSM_MIPI_NOVATEK_BOE_CMD_WVGA_PT) \
|| defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_CMD_QHD_PT)
if(mdp_lut_push) {
mipi_dsi_mdp_busy_wait();
mdp_lut_enable();
}
#endif
if (need_ov_wait) {
pr_debug("#### %s: wait4ov\n", __func__);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
outpdw(MDP_BASE + 0x0004, 0);
mb();
mdp4_dsi_cmd_wait4ov(0);
}
if (pipe->ov_blt_addr) {
if (vctrl->blt_end) {
vctrl->blt_end = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
}
}
if (vctrl->blt_change) {
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
vctrl->blt_change = 0;
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
/* tx dcs command if had any */
mipi_dsi_cmdlist_commit(1);
mdp4_mixer_stage_commit(mixer);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_cmd_blt_ov_update(pipe);
pipe->ov_cnt++;
vctrl->ov_koff++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
} else {
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
vctrl->dmap_koff++;
}
pr_debug("%s: kickoff, pid=%d\n", __func__, current->pid);
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
mb();
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait)
mdp4_dsi_cmd_wait4vsync(0);
return cnt;
}
int disp_ext_board_detect_board(struct msm_fb_data_type *mfd)
{
int i;
int ret = 0;
int panel_found;
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
uint32_t data;
#else
uint32_t data[2];
#endif
DISP_LOCAL_LOG_EMERG("DISP disp_ext_board_detect_board S\n");
if( panel_detection != 0 ) {
pr_debug("%s:panel Checked\n", __func__);
DISP_LOCAL_LOG_EMERG("%s:panel Checked\n", __func__);
return panel_detection;
}
mipi_dsi_op_mode_config(DSI_CMD_MODE);
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
/* cmd1 select */
ret = disp_ext_board_cmd_tx( detect_board_cmd1_select, sizeof(detect_board_cmd1_select), 0 );
if ( ret != 0 ) {
pr_err("%s:command send err1\n", __func__);
mipi_dsi_op_mode_config(mfd->panel_info.mipi.mode);
light_led_disp_set(LIGHT_MAIN_WLED_LCD_DIS);
panel_detection = -1;
return panel_detection;
}
#endif
#ifdef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
mipi_dsi_clk_cfg(1);
#endif
panel_found = 0;
for( i = 0 ; i < DETECT_BOARD_NUM ; i++ ) {
/* MIPI_DSI_MRPS, Maximum Return Packet Size */
if (!mfd->panel_info.mipi.no_max_pkt_size) {
disp_ext_board_cmd_tx( maximum_return_seze_set , sizeof(maximum_return_seze_set), 0 );
}
ret = disp_ext_board_cmd_tx( detect_board_mipi_lane_read , sizeof(detect_board_mipi_lane_read), 5 );
if ( ret != 0 ) {
pr_err("%s:ack no receive\n", __func__);
mipi_dsi_op_mode_config(mfd->panel_info.mipi.mode);
light_led_disp_set(LIGHT_MAIN_WLED_LCD_DIS);
panel_detection = -1;
return panel_detection;
}
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
data = (uint32)MIPI_INP(MIPI_DSI_BASE + 0x68);
if( ((data >> 16) & 0xFF) == 0x02 ) {
panel_found = 1;
break;
}
#else
data[0] = (uint32)MIPI_INP(MIPI_DSI_BASE + 0x6C);
data[1] = (uint32)MIPI_INP(MIPI_DSI_BASE + 0x68);
data[1] &= 0xffff0000;
pr_info("%s: device code=%04x %04x\n",
__func__,
data[0],
data[1]
);
if ( (data[0] == 0x01010101)&&(data[1] == 0x00ff0000) ) {
panel_found = 1;
break;
}
else if ( (data[0] == 0x02020202)&&(data[1] == 0x00ff0000) ) {
panel_found = 2;
break;
}
#endif
}
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
if( panel_found != 1 ) {
#else
mipi_dsi_clk_cfg(0);
if( panel_found != 1 && panel_found != 2) {
#endif
pr_debug("%s:panel not found\n", __func__);
DISP_LOCAL_LOG_EMERG("%s:panel not found 2\n", __func__);
mipi_dsi_op_mode_config(mfd->panel_info.mipi.mode);
light_led_disp_set(LIGHT_MAIN_WLED_LCD_DIS);
panel_detection = -1;
return panel_detection;
}
pr_debug("%s:panel found\n", __func__);
DISP_LOCAL_LOG_EMERG("%s:panel found\n", __func__);
mipi_dsi_op_mode_config(mfd->panel_info.mipi.mode);
light_led_disp_set(LIGHT_MAIN_WLED_LCD_EN);
DISP_LOCAL_LOG_EMERG("DISP disp_ext_board_detect_board E\n");
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
panel_detection = 1;
#else
panel_detection = panel_found;
#endif
return panel_detection;
}
int disp_ext_board_get_panel_detect(void)
{
return panel_detection;
}
int disp_ext_blc_mode_select( uint8_t mode )
{
struct msm_fb_data_type *mfd;
DISP_LOCAL_LOG_EMERG("DISP mipi_novatek_wxga_cabc_mode_select mode=%d S\n",mode);
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_mipitx_lock();
disp_ext_util_disp_local_lock();
#endif /* CONFIG_DISP_EXT_UTIL */
if( disp_ext_util_get_disp_state() != LOCAL_DISPLAY_ON ) {
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
pr_err("%s:panel off\n", __func__);
return -1;
}
if( mode > 0x01 ) {
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
pr_err("%s:parameter err\n", __func__);
return -1;
}
if( select_mode_ctrl == mode ) {
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
DISP_LOCAL_LOG_EMERG("%s:Request a double. state=%d,req=%d\n",__func__,select_mode_ctrl,mode);
return 0;
}
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
mfd = mipi_novatek_wxga_get_mfd();
#else
mfd = mipi_renesas_cm_get_mfd();
#endif
if( mfd == NULL ) {
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
pr_err("%s:mfd == NULL\n", __func__);
return -1;
}
select_mode_ctrl=mode;
msm_fb_pan_lock();
msm_fb_ioctl_ppp_lock();
msm_fb_ioctl_lut_lock();
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
mipi_dsi_mdp_busy_wait(mfd);
#else
mdp4_dsi_cmd_busy();
mipi_dsi_mdp_busy_wait();
#endif
if( mode == 0 ) {
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
cabc_change[1] = 0;
#else
cabc_mode_select_cmds = renesas_cm_blc_off_cmds;
cabc_mode_select_cmds_size = ARRAY_SIZE(renesas_cm_blc_off_cmds);
#endif
}
else {
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
cabc_change[1] = select_mode;
#else
cabc_mode_select_cmds = renesas_cm_blc_on_cmds;
cabc_mode_select_cmds_size = ARRAY_SIZE(renesas_cm_blc_on_cmds);
#endif
}
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
pr_debug("%s:cabc_change[%d,%d]\n", __func__,cabc_change[0],cabc_change[1]);
DISP_LOCAL_LOG_EMERG("%s:cabc_change[%d,%d]\n", __func__,cabc_change[0],cabc_change[1]);
#endif
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
mipi_dsi_cmds_tx(mfd, &disp_ext_blc_tx_buf,
cabc_mode_select_cmds,
ARRAY_SIZE(cabc_mode_select_cmds));
#else
mipi_set_tx_power_mode(0);
mipi_dsi_clk_cfg(1);
mipi_dsi_cmds_tx(&disp_ext_blc_tx_buf,
cabc_mode_select_cmds,
cabc_mode_select_cmds_size);
mipi_dsi_clk_cfg(0);
#endif
udelay(1);
msm_fb_ioctl_lut_unlock();
msm_fb_ioctl_ppp_unlock();
msm_fb_pan_unlock();
#ifdef CONFIG_DISP_EXT_UTIL
disp_ext_util_disp_local_unlock();
disp_ext_util_mipitx_unlock();
#endif /* CONFIG_DISP_EXT_UTIL */
pr_debug("%s:cabc select\n", __func__);
DISP_LOCAL_LOG_EMERG("DISP mipi_novatek_wxga_cabc_mode_select E\n");
return 0;
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int clk_set_on = 0;
#if defined(CONFIG_MACH_JAGUAR)
static int logo;
#endif
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
#if defined(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_WVGA_PT) || \
defined(CONFIG_FB_MSM_MIPI_NOVATEK_BOE_CMD_WVGA_PT)
if (!is_lcd_connected)
return;
#endif
mutex_lock(&vctrl->update_lock);
if (atomic_read(&vctrl->suspend)) {
#if defined(CONFIG_MACH_JAGUAR)
if (!logo || poweroff_charging ) {
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR,
MDP_PRIM_RDPTR_TERM);
logo = 1;
} else {
pr_err("%s: mdp clocks disabled\n", __func__);
mutex_unlock(&vctrl->update_lock);
return;
}
#else
mutex_unlock(&vctrl->update_lock);
pr_err("%s: suspended, no more pan display\n", __func__);
return;
#endif
}
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
}
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_err("%s: warning, clock off while pan display\n", __func__);
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
mutex_unlock(&vctrl->update_lock);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mutex_lock(&mfd->dma->ov_mutex);
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
static int set_sre(int level)
{
int ret = 0;
pr_info("%s sre level = %d\n",__func__,level);
mutex_lock(&sre_mutex);
/*OPPO 2013-10-18 zhzhyon Add for reason*/
#ifdef PANEL_CABC
if((cabc_mode == CABC_CLOSE) && level)
{
printk(KERN_INFO "cabc is off,don't allow to set sre\n");
sre_level = level;
mutex_unlock(&sre_mutex);
return 0;
}
#endif
/*OPPO 2013-10-18 zhzhyon Add end*/
/*OPPO 2013-10-11 zhzhyon Add for reason*/
if(flag_lcd_off == true)
{
printk(KERN_INFO "lcd is off,don't allow to set sre\n");
sre_level = level;
mutex_unlock(&sre_mutex);
return 0;
}
/*OPPO 2013-10-11 zhzhyon Add end*/
mipi_dsi_clk_cfg(1);
mipi_set_tx_power_mode(0);
switch(level)
{
case 0:
sre_off[1] = sre_off[1] | cabc_mode;
mipi_dsi_cmds_tx(&orise_tx_buf, sre_off_sequence,
ARRAY_SIZE(sre_off_sequence));
sre_off[1] = 0x00;
sre_mode = SRE_CLOSE;
break;
case 1:
sre_weak_mode[1] = sre_weak_mode[1] | cabc_mode;
mipi_dsi_cmds_tx(&orise_tx_buf, sre_weak_mode_sequence,
ARRAY_SIZE(sre_weak_mode_sequence));
sre_weak_mode[1] = 0x50;
sre_mode = SRE_LOW_MODE;
break;
case 2:
sre_middle_mode[1] = sre_middle_mode[1] | cabc_mode;
mipi_dsi_cmds_tx(&orise_tx_buf, sre_middle_mode_sequence,
ARRAY_SIZE(sre_middle_mode_sequence));
sre_middle_mode[1] = 0x60;
sre_mode = SRE_MIDDLE_MODE;
break;
case 3:
sre_strong_mode[1] = sre_strong_mode[1] | cabc_mode;
mipi_dsi_cmds_tx(&orise_tx_buf, sre_strong_mode_sequence,
ARRAY_SIZE(sre_strong_mode_sequence));
sre_strong_mode[1] = 0x70;
sre_mode = SRE_HIGH_MODE;
break;
case 4:
sre_manual_mode[1] = sre_manual_mode[1] | cabc_mode;
mipi_dsi_cmds_tx(&orise_tx_buf, sre_manual_mode_sequence,
ARRAY_SIZE(sre_manual_mode_sequence));
sre_manual_mode[1] = 0x40;
default:
pr_err("%s Level %d is not supported!\n",__func__,level);
ret = -1;
break;
}
mipi_dsi_clk_cfg(0);
mipi_set_tx_power_mode(1);
sre_level = sre_mode;
mutex_unlock(&sre_mutex);
return ret;
}
void disp_ext_refresh_err_report_check(struct msm_fb_data_type *mfd)
{
struct dsi_cmd_desc dm_dsi_cmds;
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
char mipi_reg;
#else
char mipi_reg[2];
#endif
int ret;
if(err_report_chek_count < 1) {
err_report_chek_count++;
return;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK,MDP_BLOCK_POWER_ON, FALSE);
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds));
mipi_reg = 0xAB;
dm_dsi_cmds.dtype = DTYPE_DCS_READ; /* Command type */
dm_dsi_cmds.last = 1; /* Last command */
dm_dsi_cmds.vc = 0; /* Virtual Channel */
dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */
dm_dsi_cmds.wait = 0; /* wait response by msleep() */
dm_dsi_cmds.dlen = 1; /* Data length */
dm_dsi_cmds.payload = &mipi_reg; /* Data */
if (mdp_rev >= MDP_REV_41) {
mutex_lock(&mfd->dma->ov_mutex);
} else {
down(&mfd->dma->mutex);
}
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
mipi_dsi_mdp_busy_wait();
mdp4_dsi_clock_mod();
mipi_dsi_op_mode_config(DSI_CMD_MODE);
/* LowSpeed */
mipi_set_tx_power_mode(1);
ret = mipi_dsi_cmds_rx(mfd, &refresh_dsi_buff_tp, &refresh_dsi_buff_rp, &dm_dsi_cmds, 2);
/* HighSpeed */
mipi_set_tx_power_mode(0);
mipi_dsi_op_mode_config(mfd->panel_info.mipi.mode);
if (mdp_rev >= MDP_REV_41) {
mutex_unlock(&mfd->dma->ov_mutex);
} else {
up(&mfd->dma->mutex);
}
#else
mipi_dsi_clk_cfg(1);
memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds));
mipi_reg[0] = 0xB0;
mipi_reg[1] = 0x04;
dm_dsi_cmds.dtype = DTYPE_GEN_WRITE2; /* Command type */
dm_dsi_cmds.last = 1; /* Last command */
dm_dsi_cmds.vc = 0; /* Virtual Channel */
dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */
dm_dsi_cmds.wait = 0; /* wait response by msleep() */
dm_dsi_cmds.dlen = 2; /* Data length */
dm_dsi_cmds.payload = mipi_reg; /* Data */
if (mdp_rev >= MDP_REV_41) {
mutex_lock(&mfd->dma->ov_mutex);
} else {
down(&mfd->dma->mutex);
}
mdp4_dsi_cmd_busy();
mipi_dsi_mdp_busy_wait();
mdp4_dsi_clock_mod();
mipi_dsi_op_mode_config(DSI_CMD_MODE);
mipi_set_tx_power_mode(0);
mipi_dsi_cmds_tx(&refresh_dsi_buff_tp, &dm_dsi_cmds, 1);
memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds));
mipi_reg[0] = 0xB5;
dm_dsi_cmds.dtype = DTYPE_GEN_READ1; /* Command type */
dm_dsi_cmds.last = 1; /* Last command */
dm_dsi_cmds.vc = 0; /* Virtual Channel */
dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */
dm_dsi_cmds.wait = 0; /* wait response by msleep() */
dm_dsi_cmds.dlen = 1; /* Data length */
dm_dsi_cmds.payload = mipi_reg; /* Data */
mdp4_dsi_clock_mod();
mipi_dsi_op_mode_config(DSI_CMD_MODE);
mipi_set_tx_power_mode(0);
ret = mipi_dsi_cmds_rx(
mfd, &refresh_dsi_buff_tp, &refresh_dsi_buff_rp, &dm_dsi_cmds, 3);
if( ret == 0 ||
refresh_dsi_buff_rp.data[0] != 0 ||
refresh_dsi_buff_rp.data[1] != 0 ||
refresh_dsi_buff_rp.data[2] != 0 )
{
disp_ext_reflesh_set_sw(1);
}
memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds));
mipi_reg[0] = 0x0A;
dm_dsi_cmds.dtype = DTYPE_DCS_READ; /* Command type */
dm_dsi_cmds.last = 1; /* Last command */
dm_dsi_cmds.vc = 0; /* Virtual Channel */
dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */
dm_dsi_cmds.wait = 0; /* wait response by msleep() */
dm_dsi_cmds.dlen = 1; /* Data length */
dm_dsi_cmds.payload = mipi_reg; /* Data */
mdp4_dsi_clock_mod();
mipi_dsi_op_mode_config(DSI_CMD_MODE);
mipi_set_tx_power_mode(1);
ret = mipi_dsi_cmds_rx(
mfd, &refresh_dsi_buff_tp, &refresh_dsi_buff_rp, &dm_dsi_cmds, 1);
if( ret == 0 || refresh_dsi_buff_rp.data[0] != 0x1c )
{
disp_ext_reflesh_set_sw(1);
}
memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds));
mipi_reg[0] = 0xB0;
mipi_reg[1] = 0x03;
dm_dsi_cmds.dtype = DTYPE_GEN_WRITE2; /* Command type */
dm_dsi_cmds.last = 1; /* Last command */
dm_dsi_cmds.vc = 0; /* Virtual Channel */
dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */
dm_dsi_cmds.wait = 0; /* wait response by msleep() */
dm_dsi_cmds.dlen = 2; /* Data length */
dm_dsi_cmds.payload = mipi_reg; /* Data */
mdp4_dsi_clock_mod();
mipi_dsi_op_mode_config(DSI_CMD_MODE);
mipi_set_tx_power_mode(1);
mipi_dsi_cmds_tx(&refresh_dsi_buff_tp, &dm_dsi_cmds, 1);
mipi_dsi_op_mode_config(mfd->panel_info.mipi.mode);
if (mdp_rev >= MDP_REV_41) {
mutex_unlock(&mfd->dma->ov_mutex);
} else {
up(&mfd->dma->mutex);
}
mipi_dsi_clk_cfg(0);
#endif
mdp_pipe_ctrl(MDP_CMD_BLOCK,MDP_BLOCK_POWER_OFF, FALSE);
#ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM
if( ret == 0 || refresh_dsi_buff_rp.data[0] != 0 || refresh_dsi_buff_rp.data[1] != 0 ) {
disp_ext_reflesh_set_sw(1);
}
#endif
}
int mdp4_dsi_cmd_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
int undx;
int need_wait, cnt;
unsigned long flags;
int mixer = 0;
pr_debug("%s+: pid=%d\n", __func__, current->pid);
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return ret;
}
need_wait = 0;
mutex_lock(&vctrl->update_lock);
wake_up_interruptible_all(&vctrl->wait_queue);
pr_debug("%s: clk=%d pan=%d\n", __func__,
vctrl->clk_enabled, vctrl->pan_display);
if (vctrl->clk_enabled)
need_wait = 1;
mutex_unlock(&vctrl->update_lock);
cnt = 0;
if (need_wait) {
while (vctrl->clk_enabled) {
msleep(20);
cnt++;
if (cnt > 10)
break;
}
}
if (cnt > 10) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->clk_enabled = 0;
vctrl->expire_tick = 0;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mipi_dsi_clk_cfg(0);
mdp_clk_ctrl(0);
pr_err("%s: Error, SET_CLK_OFF by force\n", __func__);
}
if (vctrl->vsync_enabled) {
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
vctrl->vsync_enabled = 0;
}
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dsi_cmd_pipe_clean(vp);
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mixer = pipe->mixer_num;
mdp4_overlay_unset_mixer(mixer);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 1);
}
}
atomic_set(&vctrl->suspend, 1);
/*
* clean up ion freelist
* there need two stage to empty ion free list
* therefore need call unmap freelist twice
*/
mdp4_overlay_iommu_unmap_freelist(mixer);
mdp4_overlay_iommu_unmap_freelist(mixer);
mutex_unlock(&mfd->dma->ov_mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
static int set_cabc(int level)
{
int ret = 0;
pr_info("%s Neal level = %d\n",__func__,level);
set_backlight_pwm(1);
mutex_lock(&cabc_mutex);
/*OPPO 2013-10-11 zhzhyon Add for reason*/
if(flag_lcd_off == true)
{
printk(KERN_INFO "lcd is off,don't allow to set cabc\n");
cabc_mode = level;
mutex_unlock(&cabc_mutex);
return 0;
}
/*OPPO 2013-10-11 zhzhyon Add end*/
mipi_dsi_clk_cfg(1);
mipi_set_tx_power_mode(0);
/*OPPO 2013-10-18 zhzhyon Add for reason*/
#ifdef PANEL_SRE
if(level && (sre_level != sre_mode) && sre_level)
{
mipi_dsi_cmds_tx(&orise_tx_buf, sre_strong_mode_sequence,
ARRAY_SIZE(sre_strong_mode_sequence));
sre_mode = SRE_HIGH_MODE;
}
#endif
/*OPPO 2013-10-18 zhzhyon Add end*/
switch(level)
{
case 0:/*
mipi_dsi_cmds_tx(&orise_tx_buf, cabc_off_sequence,
ARRAY_SIZE(cabc_off_sequence));
*/
set_backlight_pwm(0);
cabc_mode = CABC_CLOSE;
/*OPPO 2013-10-18 zhzhyon Add for reason*/
#ifdef PANEL_SRE
sre_mode = SRE_CLOSE;
#endif
/*OPPO 2013-10-18 zhzhyon Add end*/
break;
case 1:
mipi_dsi_cmds_tx(&orise_tx_buf, cabc_user_interface_image_sequence,
ARRAY_SIZE(cabc_user_interface_image_sequence));
cabc_mode = CABC_LOW_MODE;
break;
case 2:
mipi_dsi_cmds_tx(&orise_tx_buf, cabc_still_image_sequence,
ARRAY_SIZE(cabc_still_image_sequence));
cabc_mode = CABC_MIDDLE_MODE;
break;
case 3:
mipi_dsi_cmds_tx(&orise_tx_buf, cabc_video_image_sequence,
ARRAY_SIZE(cabc_video_image_sequence));
cabc_mode = CABC_HIGH_MODE;
break;
default:
pr_err("%s Leavel %d is not supported!\n",__func__,level);
ret = -1;
break;
}
//mipi_set_tx_power_mode(1);
mipi_dsi_clk_cfg(0);
mutex_unlock(&cabc_mutex);
return ret;
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
/* make sure dsi clk is on so that
* dcs commands can be sent
*/
mipi_dsi_clk_cfg(1);
/* make sure dsi_cmd_mdp is idle */
mipi_dsi_cmd_mdp_busy();
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
