void __init time_init(void)
{
#ifdef CONFIG_HR_SCHED_CLOCK
if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
write_c0_count(0);
#endif
plat_time_init();
if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
init_mips_clocksource();
}
void __init time_init(void)
{
plat_time_init();
if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
init_mips_clocksource();
}
/*
* First C code run on the secondary CPUs after being started up by
* the master.
*/
asmlinkage __cpuinit void start_secondary(void)
{
unsigned int cpu;
#ifdef CONFIG_MIPS_MT_SMTC
/* Only do cpu_probe for first TC of CPU */
if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
#endif /* CONFIG_MIPS_MT_SMTC */
cpu_probe();
cpu_report();
per_cpu_trap_init();
mips_clockevent_init();
prom_init_secondary();
/*
* XXX parity protection should be folded in here when it's converted
* to an option instead of something based on .cputype
*/
calibrate_delay();
preempt_disable();
cpu = smp_processor_id();
cpu_data[cpu].udelay_val = loops_per_jiffy;
prom_smp_finish();
cpu_set(cpu, cpu_callin_map);
cpu_idle();
}
void __init time_init(void)
{
#ifdef CONFIG_MET
#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK
if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
write_c0_count(0);
#endif
#endif
plat_time_init();
/*
* The use of the R4k timer as a clock event takes precedence;
* if reading the Count register might interfere with the timer
* interrupt, then we don't use the timer as a clock source.
* We may still use the timer as a clock source though if the
* timer interrupt isn't reliable; the interference doesn't
* matter then, because we don't use the interrupt.
*/
if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug())
init_mips_clocksource();
}
void __init time_init(void)
{
plat_time_init();
/*
* The use of the R4k timer as a clock event takes precedence;
* if reading the Count register might interfere with the timer
* interrupt, then we don't use the timer as a clock source.
* We may still use the timer as a clock source though if the
* timer interrupt isn't reliable; the interference doesn't
* matter then, because we don't use the interrupt.
*/
if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug())
init_mips_clocksource();
}
