static void
mips_mask_soft_irq(void *source)
{
uintptr_t irq = (uintptr_t)source;
mips_wr_status(mips_rd_status() & ~((1 << irq) << 8));
}
void
platform_init_ap(int cpuid)
{
uint32_t status;
register_t hwrena;
u_int clock_int_mask;
KASSERT(cpuid < MAXCPU, ("%s: invalid CPU id %d", __func__, cpuid));
/* Make sure coprocessors are enabled. */
status = mips_rd_status();
status |= (MIPS_SR_COP_0_BIT | MIPS_SR_COP_1_BIT);
#if defined(CPU_CHERI)
status |= MIPS_SR_COP_2_BIT;
#endif
mips_wr_status(status);
/* Enable HDWRD instruction in userspace. */
hwrena = mips_rd_hwrena();
hwrena |= (MIPS_HWRENA_CC | MIPS_HWRENA_CCRES | MIPS_HWRENA_CPUNUM);
mips_wr_hwrena(hwrena);
/*
* Enable per-thread timer.
*/
clock_int_mask = hard_int_mask(5);
set_intr_mask(clock_int_mask);
}
static void
mips_unmask_hard_irq(void *source)
{
uintptr_t irq = (uintptr_t)source;
mips_wr_status(mips_rd_status() | (((1 << irq) << 8) << 2));
}
/*
* Initialize the hardware exception vectors, and the jump table used to
* call locore cache and TLB management functions, based on the kind
* of CPU the kernel is running on.
*/
void
mips_vector_init(void)
{
/*
* Make sure that the Wait region logic is not been
* changed
*/
if (MipsWaitEnd - MipsWaitStart != 16)
panic("startup: MIPS wait region not correct");
/*
* Copy down exception vector code.
*/
if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
panic("startup: UTLB code too large");
if (MipsCacheEnd - MipsCache > 0x80)
panic("startup: Cache error code too large");
bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
/*
* XXXRW: Why don't we install the XTLB handler for all 64-bit
* architectures?
*/
#if defined(__mips_n64) || defined(CPU_RMI) || defined(CPU_NLM) || defined(CPU_BERI) || defined(CPU_CHERI)
/* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
#endif
bcopy(MipsException, (void *)MIPS_GEN_EXC_VEC,
MipsExceptionEnd - MipsException);
bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC,
MipsCacheEnd - MipsCache);
#ifdef CPU_CHERI
bcopy(CHERICCallVector, (void *)CHERI_CCALL_EXC_VEC,
CHERICCallVectorEnd - CHERICCallVector);
#endif
/*
* Clear out the I and D caches.
*/
mips_icache_sync_all();
mips_dcache_wbinv_all();
/*
* Mask all interrupts. Each interrupt will be enabled
* when handler is installed for it
*/
set_intr_mask(0);
/* Clear BEV in SR so we start handling our own exceptions */
mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
}
/*
* Initialize the hardware exception vectors, and the jump table used to
* call locore cache and TLB management functions, based on the kind
* of CPU the kernel is running on.
*/
void
mips_vector_init(void)
{
/*
* Make sure that the Wait region logic is not been
* changed
*/
if (MipsWaitEnd - MipsWaitStart != 16)
panic("startup: MIPS wait region not correct");
/*
* Copy down exception vector code.
*/
if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
panic("startup: UTLB code too large");
if (MipsCacheEnd - MipsCache > 0x80)
panic("startup: Cache error code too large");
bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
#ifdef __mips_n64
bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
#endif
bcopy(MipsException, (void *)MIPS_GEN_EXC_VEC,
MipsExceptionEnd - MipsException);
bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC,
MipsCacheEnd - MipsCache);
/*
* Clear out the I and D caches.
*/
mips_icache_sync_all();
mips_dcache_wbinv_all();
/*
* Mask all interrupts. Each interrupt will be enabled
* when handler is installed for it
*/
set_intr_mask(0);
/* Clear BEV in SR so we start handling our own exceptions */
mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
}
void
platform_init_secondary(int cpuid)
{
device_t ic;
int ipi;
ipi = platform_ipi_hardintr_num();
/* XXX: single core/pic */
ic = SLIST_FIRST(&fdt_ic_list_head)->dev;
FDT_IC_SETUP_IPI(ic, cpuid, ipi);
picmap[cpuid] = ic;
/* Unmask the interrupt */
if (cpuid != 0)
mips_wr_status(mips_rd_status() | (((1 << ipi) << 8) << 2));
}
/*
* Initialize the hardware exception vectors, and the jump table used to
* call locore cache and TLB management functions, based on the kind
* of CPU the kernel is running on.
*/
void
mips_vector_init(void)
{
/*
* Copy down exception vector code.
*/
if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
panic("startup: UTLB code too large");
if (MipsCacheEnd - MipsCache > 0x80)
panic("startup: Cache error code too large");
bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
#if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM)
/* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
#endif
bcopy(MipsException, (void *)MIPS3_GEN_EXC_VEC,
MipsExceptionEnd - MipsException);
bcopy(MipsCache, (void *)MIPS3_CACHE_ERR_EXC_VEC,
MipsCacheEnd - MipsCache);
/*
* Clear out the I and D caches.
*/
mips_icache_sync_all();
mips_dcache_wbinv_all();
/*
* Mask all interrupts. Each interrupt will be enabled
* when handler is installed for it
*/
set_intr_mask(0);
/* Clear BEV in SR so we start handling our own exceptions */
mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
}
static inline void
pic_irq_mask(struct mips_pic_softc *sc, u_int irq)
{
mips_wr_status(mips_rd_status() & ~((1 << irq) << 8));
}
