/**
* @brief Return the value of the XSCOM BAR that the driver is using
*/
uint64_t get_master_bar( void )
{
return mm_virt_to_phys(g_masterProcVirtAddr);
}
/**
* @brief Starts OCCs on all Processors in the node
* This is intended to be used for AVP testing.
*
* @param[out] o_failedOccTarget: Pointer to the target failing
* loadnStartAllOccs
* @param[in] i_useSRAM: bool - use SRAM for OCC image, ie during IPL
* true if during IPL, false if at end of IPL (default)
* @return errlHndl_t Error log if OCC load failed
*/
errlHndl_t loadnStartAllOccs(TARGETING::Target *& o_failedOccTarget,
bool i_useSRAM)
{
errlHndl_t l_errl = NULL;
void* homerVirtAddrBase = NULL;
uint64_t homerPhysAddrBase = VMM_HOMER_REGION_START_ADDR;
bool winkle_loaded = false;
TRACUCOMP( g_fapiTd,
ENTER_MRK"loadnStartAllOccs(%d)", i_useSRAM);
do {
#ifndef __HOSTBOOT_RUNTIME
//OCC requires the build_winkle_images library
if ( !VFS::module_is_loaded( "libbuild_winkle_images.so" ) )
{
l_errl = VFS::module_load( "libbuild_winkle_images.so" );
if ( l_errl )
{
// load module returned with errl set
TRACFCOMP( g_fapiTd,ERR_MRK"loadnStartAllOccs: Could not load build_winkle module" );
// break from do loop if error occured
break;
}
winkle_loaded = true;
}
assert(VMM_HOMER_REGION_SIZE <= THIRTYTWO_GB,
"loadnStartAllOccs: Unsupported HOMER Region size");
if (!i_useSRAM)
{
//If running Sapphire need to place this at the top of memory
if(TARGETING::is_sapphire_load())
{
homerPhysAddrBase = TARGETING::get_top_mem_addr();
assert (homerPhysAddrBase != 0,
"loadnStartAllOccs: Top of memory was 0!");
homerPhysAddrBase -= VMM_ALL_HOMER_OCC_MEMORY_SIZE;
}
TRACFCOMP( g_fapiTd, "HOMER is at %.16X", homerPhysAddrBase );
//Map entire homer region into virtual memory
homerVirtAddrBase =
mm_block_map(reinterpret_cast<void*>(homerPhysAddrBase),
VMM_HOMER_REGION_SIZE);
TRACFCOMP( g_fapiTd, "HOMER virtaddrbase %.16X", homerVirtAddrBase );
}
else
{
// malloc space big enough for all of OCC
homerVirtAddrBase = (void *)malloc(1 * MEGABYTE);
homerPhysAddrBase = mm_virt_to_phys(homerVirtAddrBase);
}
#endif
if (i_useSRAM)
{
// OCC is going into L3 and SRAM so only need 1 prime and load
// into the Master Proc
TargetService & tS = targetService();
Target * sysTarget = NULL;
tS.getTopLevelTarget( sysTarget );
assert( sysTarget != NULL );
Target* masterproc = NULL;
tS.masterProcChipTargetHandle( masterproc );
/******* SETUP AND LOAD **************/
l_errl = primeAndLoadOcc (masterproc,
homerVirtAddrBase,
homerPhysAddrBase,
i_useSRAM);
if(l_errl)
{
o_failedOccTarget = masterproc;
TRACFCOMP( g_fapiImpTd, ERR_MRK
"loadnStartAllOccs:primeAndLoadOcc failed");
free(homerVirtAddrBase);
break;
}
/********* START OCC *************/
l_errl = HBOCC::startOCC (masterproc, NULL, o_failedOccTarget);
// it either started or errored; either way, free the memory
free(homerVirtAddrBase);
if (l_errl)
{
TRACFCOMP( g_fapiImpTd, ERR_MRK"loadnStartAllOccs: startOCC failed");
break;
}
}
else
{
TargetHandleList procChips;
getAllChips(procChips, TYPE_PROC, true);
if(procChips.size() == 0)
{
TRACFCOMP( g_fapiTd,INFO_MRK"loadnStartAllOccs: No processors found" );
//We'll never get this far in the IPL without any processors,
// so just exit.
break;
}
TRACUCOMP( g_fapiTd,
INFO_MRK"loadnStartAllOccs: %d procs found",
procChips.size());
TargetHandleList::iterator itr1 = procChips.begin();
//The OCC Procedures require processors within a DCM be
//setup together. So, first checking if any proc has
//DCM installed attribute set. If not, we can iterate
//over the list in any order.
//If DCM installed is set, we work under the assumption
//that each nodeID is a DCM. So sort the list by NodeID
//then call OCC Procedures on NodeID pairs.
if(0 ==
(*itr1)->getAttr<ATTR_PROC_DCM_INSTALLED>())
{
TRACUCOMP( g_fapiTd,
INFO_MRK"loadnStartAllOccs: non-dcm path entered");
for (TargetHandleList::iterator itr = procChips.begin();
itr != procChips.end();
++itr)
{
/******* SETUP AND LOAD **************/
l_errl = primeAndLoadOcc (*itr,
homerVirtAddrBase,
homerPhysAddrBase,
i_useSRAM);
if(l_errl)
{
o_failedOccTarget = *itr;
TRACFCOMP( g_fapiImpTd, ERR_MRK
"loadnStartAllOccs:primeAndLoadOcc failed");
break;
}
/********* START OCC *************/
l_errl = HBOCC::startOCC (*itr, NULL, o_failedOccTarget);
if (l_errl)
{
TRACFCOMP( g_fapiImpTd, ERR_MRK"loadnStartAllOccs: startOCC failed");
break;
}
}
if (l_errl)
{
break;
}
}
else
{
TRACUCOMP( g_fapiTd,
INFO_MRK"loadnStartAllOccs: Following DCM Path");
std::sort(procChips.begin(),
procChips.end(),
orderByNodeAndPosition);
TRACUCOMP( g_fapiTd,
INFO_MRK"loadnStartAllOccs: procChips list sorted");
for (TargetHandleList::iterator itr = procChips.begin();
itr != procChips.end();
++itr)
{
TRACUCOMP( g_fapiImpTd, INFO_MRK"loadnStartAllOccs: Insepcting first target" );
Target* targ0 = *itr;
Target* targ1 = NULL;
TRACUCOMP( g_fapiImpTd, INFO_MRK
"loadnStartAllOccs: Cur target nodeID=%d",
targ0->getAttr<ATTR_FABRIC_NODE_ID>());
//if the next target in the list is in the same node
// they are on the same DCM, so bump itr forward
// and update targ1 pointer
if((itr+1) != procChips.end())
{
TRACUCOMP( g_fapiImpTd, INFO_MRK
"loadnStartAllOccs: n+1 target nodeID=%d",
((*(itr+1))->getAttr<ATTR_FABRIC_NODE_ID>())
);
if((targ0->getAttr<ATTR_FABRIC_NODE_ID>()) ==
((*(itr+1))->getAttr<ATTR_FABRIC_NODE_ID>()))
{
itr++;
targ1 = *itr;
}
}
/********** Setup and load targ0 ***********/
l_errl = primeAndLoadOcc (targ0,
homerVirtAddrBase,
homerPhysAddrBase,
i_useSRAM);
if(l_errl)
{
o_failedOccTarget = targ0;
TRACFCOMP( g_fapiImpTd, ERR_MRK
"loadnStartAllOccs: "
"primeAndLoadOcc failed on targ0");
break;
}
/*********** Setup and load targ1 **********/
l_errl = primeAndLoadOcc (targ1,
homerVirtAddrBase,
homerPhysAddrBase,
i_useSRAM);
if(l_errl)
{
o_failedOccTarget = targ1;
TRACFCOMP( g_fapiImpTd, ERR_MRK
"loadnStartAllOccs: "
"primeAndLoadOcc failed on targ1");
break;
}
/*********** Start OCC *******************/
l_errl = HBOCC::startOCC (targ0, targ1, o_failedOccTarget);
if (l_errl)
{
TRACFCOMP( g_fapiImpTd, ERR_MRK
"loadnStartAllOccs: start failed");
break;
}
}
if (l_errl)
{
break;
}
}
}
} while(0);
errlHndl_t l_tmpErrl = NULL;
//Unless HTMGT is in use, there are no further accesses to HOMER memory
//required during the IPL
#ifndef CONFIG_HTMGT
if(homerVirtAddrBase)
{
int rc = 0;
rc = mm_block_unmap(homerVirtAddrBase);
if (rc != 0)
{
/*@
* @errortype
* @moduleid fapi::MOD_OCC_LOAD_START_ALL_OCCS
* @reasoncode fapi::RC_MM_UNMAP_ERR
* @userdata1 Return Code
* @userdata2 Unmap address
* @devdesc mm_block_unmap() returns error
* @custdesc A problem occurred during the IPL
* of the system.
*/
l_tmpErrl =
new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_OCC_LOAD_START_ALL_OCCS,
fapi::RC_MM_UNMAP_ERR,
rc,
reinterpret_cast<uint64_t>
(homerVirtAddrBase));
if(l_tmpErrl)
{
if(l_errl)
{
errlCommit( l_tmpErrl, HWPF_COMP_ID );
}
else
{
l_errl = l_tmpErrl;
}
}
}
}
#endif
//make sure we always unload the module
if (winkle_loaded)
{
l_tmpErrl = VFS::module_unload( "libbuild_winkle_images.so" );
if ( l_tmpErrl )
{
TRACFCOMP
( g_fapiTd,ERR_MRK
"loadnStartAllOccs: Error unloading build_winkle module"
);
if(l_errl)
{
errlCommit( l_tmpErrl, HWPF_COMP_ID );
}
else
{
l_errl = l_tmpErrl;
}
}
}
TRACUCOMP( g_fapiTd,
EXIT_MRK"loadnStartAllOccs" );
return l_errl;
}
