void board_init()
{
int i;
/*
* This is probably not mandatory, but just in case setup
* them to state in which they exited MBM
*/
/* Stop & Reset GPTIMER1 */
modify_register32(GPTIMER1_BASE + 0x24, 0x1, 0x0);
write32(1, GPTIMER1_BASE + 0x10);
while ((read32(GPTIMER1_BASE + 0x14) & 1) != 1);
/*
* MBM boots OMAP3430 with 500 MHz.
*/
/* Unlock PLL */
modify_register32(CM_CLKEN_PLL_MPU, 0x7, 0x5);
while ((read32(CM_IDLEST_PLL_MPU) & 1) != 0);
/* Set the dividers */
modify_register32(CM_CLKSEL2_PLL_MPU, 0x1F, 0x1);
modify_register32(CM_CLKSEL1_PLL_MPU, 0x07 << 18, 0x01 << 18);
modify_register32(CM_CLKSEL1_PLL_MPU, 0x7FF << 8, 0xFA << 8);
modify_register32(CM_CLKSEL1_PLL_MPU, 0x7F, 0x0C);
/* Set frequency */
modify_register32(CM_CLKEN_PLL_MPU, 0xF << 4, 0x7 << 4);
/* Relock PLL */
i = 0;
modify_register32(CM_CLKEN_PLL_MPU, 0x7, 0x7);
while ((read32(CM_IDLEST_PLL_MPU) & 1) != 1)
{
i++;
if (i > 0x2000)
{
/* Kick it again */
i = 0;
modify_register32(CM_CLKEN_PLL_MPU, 0x7, 0x7);
}
}
/* Unlock DPPL5 */
modify_register32(CM_CLKEN2_PLL, 0x7, 0x1);
while((read32(CM_IDLEST2_CKGEN) & 1) != 0);
}
int hw_preboot() {
/* Enable USBOTG clocks */
modify_register32(CRM_AP_BASE_ADDR+0xc, 0, 1 << 12);
modify_register32(CRM_AP_BASE_ADDR+0x28, 0, 0x3 << 22);
modify_register32(CRM_AP_BASE_ADDR+0x34, 0, 0x3 << 16);
/* Reset USBOTG */
write32(0x3f, USBOTG_CTRL_BASE_ADDR+0x10);
while (read32(USBOTG_CTRL_BASE_ADDR+0x10)) {
}
/* Enable main USBOTG clock */
write32(0x1, USBOTG_CTRL_BASE_ADDR+0xc);
/* Disable SDHC1/2 clocks */
modify_register32(CRM_AP_BASE_ADDR+0x60, 0, 1 << 0);
modify_register32(CRM_AP_BASE_ADDR+0x60, 0, 1 << 8);
/* Reset EPIT */
modify_register32(EPIT1_AP_BASE_ADDR+0x0, 0x1, 0);
modify_register32(EPIT1_AP_BASE_ADDR+0x0, 0, 0x10000);
while (read32(EPIT1_AP_BASE_ADDR+0x0) & 0x10000) {
}
/* Disable and clear KPP */
write16(0xf, KPP_BASE_ADDR+0x2);
/* Stop SDMA */
write32(0xffffffff, SDMA_BASE_ADDR+0x8);
write32(0xffffffff, SDMA_BASE_ADDR+0x4);
/* Reset SDMA */
write32(0x1, SDMA_BASE_ADDR+0x24);
while (read32(SDMA_BASE_ADDR+0x28) & 0x1) {
}
/* Enable UART3 clocks */
modify_register32(CRM_AP_BASE_ADDR+0x5c, 0, 1 << 16);
}
