static int msm_hsl_console_setup(struct console *co, char *options)
{
struct uart_port *port;
unsigned int vid;
int baud = 0, flow, bits, parity;
int ret;
pr_info("%s: ir\n", __func__);
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
vid = UART_TO_MSM(port)->ver_id;
pr_info("%s ():port->line %d, ir\n", __func__, port->line);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
pm_runtime_get_noresume(port->dev);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_resume(port->dev);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
regmap[vid][UARTDM_MR2]);
if (baud < 300 || baud > 115200)
baud = 115200;
msm_hsl_set_baud_rate(port, baud);
pr_info("%s: cir port[%d] set baud=%d\n", __func__, port->line, baud);
ret = uart_set_options(port, co, baud, parity, bits, flow);
msm_hsl_reset(port);
msm_hsl_write(port, CR_PROTECTION_EN, regmap[vid][UARTDM_CR]);
msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, regmap[vid][UARTDM_CR]);
printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
port->line);
pr_info("%s ():port->line %d, ok, ir\n", __func__, port->line);
return ret;
}
static int __init msm_hsl_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud, flow, bits, parity;
int ret;
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
pm_runtime_get_noresume(port->dev);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_resume(port->dev);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
UARTDM_MR2_ADDR); /* 8N1 */
if (baud < 300 || baud > 115200)
baud = 115200;
msm_hsl_set_baud_rate(port, baud);
ret = uart_set_options(port, co, baud, parity, bits, flow);
msm_hsl_reset(port);
/* Enable transmitter */
msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
port->line);
console_uart_port = port;
b_terminal_onoff = 0;
return ret;
}
static void msm_hsl_set_termios(struct uart_port *port,
struct ktermios *termios,
struct ktermios *old)
{
unsigned long flags;
unsigned int baud, mr;
spin_lock_irqsave(&port->lock, flags);
clk_en(port, 1);
/* calculate and set baud rate */
/* [FELICA_S] [email protected] 20110419 */
/* change default baudrate for felica */
#ifdef CONFIG_LGE_FELICA
if (port->line == 3)
{
termios->c_cflag |= B460800;
baud = uart_get_baud_rate(port, termios, old, 300, 460800);
msm_hsl_set_baud_rate(port, baud);
}
else
{
baud = uart_get_baud_rate(port, termios, old, 300, 115200);
msm_hsl_set_baud_rate(port, baud);
}
#else
baud = uart_get_baud_rate(port, termios, old, 300, 460800);
msm_hsl_set_baud_rate(port, baud);
#endif
/* [FELICA_E] [email protected] 20110419 */
/* calculate parity */
mr = msm_hsl_read(port, UARTDM_MR2_ADDR);
mr &= ~UARTDM_MR2_PARITY_MODE_BMSK;
if (termios->c_cflag & PARENB) {
if (termios->c_cflag & PARODD)
mr |= ODD_PARITY;
else if (termios->c_cflag & CMSPAR)
mr |= SPACE_PARITY;
else
mr |= EVEN_PARITY;
}
/* calculate bits per char */
mr &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
switch (termios->c_cflag & CSIZE) {
case CS5:
mr |= FIVE_BPC;
break;
case CS6:
mr |= SIX_BPC;
break;
case CS7:
mr |= SEVEN_BPC;
break;
case CS8:
default:
mr |= EIGHT_BPC;
break;
}
/* calculate stop bits */
mr &= ~(STOP_BIT_ONE | STOP_BIT_TWO);
if (termios->c_cflag & CSTOPB)
mr |= STOP_BIT_TWO;
else
mr |= STOP_BIT_ONE;
/* set parity, bits per char, and stop bit */
msm_hsl_write(port, mr, UARTDM_MR2_ADDR);
/* calculate and set hardware flow control */
mr = msm_hsl_read(port, UARTDM_MR1_ADDR);
mr &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
if (termios->c_cflag & CRTSCTS) {
mr |= UARTDM_MR1_CTS_CTL_BMSK;
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
}
msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
/* Configure status bits to ignore based on termio flags. */
port->read_status_mask = 0;
if (termios->c_iflag & INPCK)
port->read_status_mask |= UARTDM_SR_PAR_FRAME_BMSK;
if (termios->c_iflag & (BRKINT | PARMRK))
port->read_status_mask |= UARTDM_SR_RX_BREAK_BMSK;
uart_update_timeout(port, termios->c_cflag, baud);
clk_en(port, 0);
spin_unlock_irqrestore(&port->lock, flags);
}
static void msm_hsl_set_termios(struct uart_port *port,
struct ktermios *termios,
struct ktermios *old)
{
unsigned long flags;
unsigned int baud, mr;
spin_lock_irqsave(&port->lock, flags);
clk_en(port, 1);
/* calculate and set baud rate */
baud = uart_get_baud_rate(port, termios, old, 300, 115200);
/* Workaround required for UART download feature.
set_termios is getting called while opening port and while
setting required baud rate using Ioctl. Adding delay allows
this feature to work. Reason is still unknown.
*/
udelay(1000);
msm_hsl_set_baud_rate(port, baud);
/* calculate parity */
mr = msm_hsl_read(port, UARTDM_MR2_ADDR);
mr &= ~UARTDM_MR2_PARITY_MODE_BMSK;
if (termios->c_cflag & PARENB) {
if (termios->c_cflag & PARODD)
mr |= ODD_PARITY;
else if (termios->c_cflag & CMSPAR)
mr |= SPACE_PARITY;
else
mr |= EVEN_PARITY;
}
/* calculate bits per char */
mr &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
switch (termios->c_cflag & CSIZE) {
case CS5:
mr |= FIVE_BPC;
break;
case CS6:
mr |= SIX_BPC;
break;
case CS7:
mr |= SEVEN_BPC;
break;
case CS8:
default:
mr |= EIGHT_BPC;
break;
}
/* calculate stop bits */
mr &= ~(STOP_BIT_ONE | STOP_BIT_TWO);
if (termios->c_cflag & CSTOPB)
mr |= STOP_BIT_TWO;
else
mr |= STOP_BIT_ONE;
/* set parity, bits per char, and stop bit */
msm_hsl_write(port, mr, UARTDM_MR2_ADDR);
/* calculate and set hardware flow control */
mr = msm_hsl_read(port, UARTDM_MR1_ADDR);
mr &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
if (termios->c_cflag & CRTSCTS) {
mr |= UARTDM_MR1_CTS_CTL_BMSK;
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
}
msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
/* Configure status bits to ignore based on termio flags. */
port->read_status_mask = 0;
if (termios->c_iflag & INPCK)
port->read_status_mask |= UARTDM_SR_PAR_FRAME_BMSK;
if (termios->c_iflag & (BRKINT | PARMRK))
port->read_status_mask |= UARTDM_SR_RX_BREAK_BMSK;
uart_update_timeout(port, termios->c_cflag, baud);
clk_en(port, 0);
spin_unlock_irqrestore(&port->lock, flags);
}
static void msm_hsl_set_termios_irda(struct uart_port *port,
struct ktermios *termios,
struct ktermios *old)
{
unsigned long flags;
unsigned int baud, mr;
unsigned int vid;
spin_lock_irqsave(&port->lock, flags);
/* calculate and set baud rate */
baud = uart_get_baud_rate(port, termios, old, 300, 460800);
msm_hsl_set_baud_rate(port, baud);
vid = UART_TO_MSM(port)->ver_id;
/* calculate parity */
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
mr &= ~UARTDM_MR2_PARITY_MODE_BMSK;
if (termios->c_cflag & PARENB) {
if (termios->c_cflag & PARODD)
mr |= ODD_PARITY;
else if (termios->c_cflag & CMSPAR)
mr |= SPACE_PARITY;
else
mr |= EVEN_PARITY;
}
/* calculate bits per char */
mr &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
switch (termios->c_cflag & CSIZE) {
case CS5:
mr |= FIVE_BPC;
break;
case CS6:
mr |= SIX_BPC;
break;
case CS7:
mr |= SEVEN_BPC;
break;
case CS8:
default:
mr |= EIGHT_BPC;
break;
}
/* calculate stop bits */
mr &= ~(STOP_BIT_ONE | STOP_BIT_TWO);
if (termios->c_cflag & CSTOPB)
mr |= STOP_BIT_TWO;
else
mr |= STOP_BIT_ONE;
/* set parity, bits per char, and stop bit */
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR2]);
/* calculate and set hardware flow control */
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
mr &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
if (termios->c_cflag & CRTSCTS) {
mr |= UARTDM_MR1_CTS_CTL_BMSK;
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
}
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
/* Configure status bits to ignore based on termio flags. */
port->read_status_mask = 0;
if (termios->c_iflag & INPCK)
port->read_status_mask |= UARTDM_SR_PAR_FRAME_BMSK;
if (termios->c_iflag & (BRKINT | PARMRK))
port->read_status_mask |= UARTDM_SR_RX_BREAK_BMSK;
uart_update_timeout(port, termios->c_cflag, baud);
spin_unlock_irqrestore(&port->lock, flags);
D("%s: irda MR is 0x%x\n", __func__, mr);
D("%s: irda baud is %d\n", __func__, baud);
/*
D("%s: irda parity is %d \n", __func__, (termios->c_cflag & PARENB)!=0?1:0);
D("%s: irda csize is %d \n", __func__,
(termios->c_cflag & CSIZE)==CS5 ? 5:
(termios->c_cflag & CSIZE)==CS6 ? 6:
(termios->c_cflag & CSIZE)==CS7 ? 7:
(termios->c_cflag & CSIZE)==CS8 ? 8:(-1));
D("%s: irda stop is %d \n", __func__, (termios->c_cflag & CSTOPB)!=0?1:0);
D("%s: irda hw-flow is %d \n", __func__, (termios->c_cflag & CRTSCTS)!=0?1:0);
D("%s: irda INPCK is %d , BRKINT is %d , PARMRK is %d \n", __func__, (termios->c_iflag & INPCK)!=0?1:0,
(termios->c_iflag & BRKINT)!=0?1:0,
(termios->c_iflag & PARMRK)!=0?1:0);
D("%s: irda xon is %d \n", __func__, (termios->c_iflag & IXON)!=0?1:0);
D("%s: irda xoff is %d \n", __func__, (termios->c_iflag & IXOFF)!=0?1:0);*/
}
static void msm_hsl_set_termios_cir(struct uart_port *port,
struct ktermios *termios,
struct ktermios *old)
{
unsigned long flags;
unsigned int baud, mr;
unsigned int vid;
spin_lock_irqsave(&port->lock, flags);
baud = uart_get_baud_rate(port, termios, old, 300, 460800);
msm_hsl_set_baud_rate(port, baud);
vid = UART_TO_MSM(port)->ver_id;
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
mr &= ~UARTDM_MR2_PARITY_MODE_BMSK;
if (termios->c_cflag & PARENB) {
if (termios->c_cflag & PARODD)
mr |= ODD_PARITY;
else if (termios->c_cflag & CMSPAR)
mr |= SPACE_PARITY;
else
mr |= EVEN_PARITY;
}
mr &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
switch (termios->c_cflag & CSIZE) {
case CS5:
mr |= FIVE_BPC;
break;
case CS6:
mr |= SIX_BPC;
break;
case CS7:
mr |= SEVEN_BPC;
break;
case CS8:
default:
mr |= EIGHT_BPC;
break;
}
mr &= ~(STOP_BIT_ONE | STOP_BIT_TWO);
if (termios->c_cflag & CSTOPB)
mr |= STOP_BIT_TWO;
else
mr |= STOP_BIT_ONE;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR2]);
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
mr &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
if (termios->c_cflag & CRTSCTS) {
mr |= UARTDM_MR1_CTS_CTL_BMSK;
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
}
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
port->read_status_mask = 0;
if (termios->c_iflag & INPCK)
port->read_status_mask |= UARTDM_SR_PAR_FRAME_BMSK;
if (termios->c_iflag & (BRKINT | PARMRK))
port->read_status_mask |= UARTDM_SR_RX_BREAK_BMSK;
uart_update_timeout(port, termios->c_cflag, baud);
spin_unlock_irqrestore(&port->lock, flags);
D("%s: cir MR is 0x%x\n", __func__, mr);
D("%s: cir baud is %d\n", __func__, baud);
}
