static int msm_serial_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct uart_port *port;
port = get_port_from_line(pdev->id);
dev_dbg(dev, "pm_runtime: resuming\n");
msm_init_clock(port);
return 0;
}
static int msm_serial_resume(struct platform_device *pdev)
{
struct uart_port *port;
port = get_port_from_line(pdev->id);
if (port) {
if (is_console(port))
msm_init_clock(port);
uart_resume_port(&msm_uart_driver, port);
}
return 0;
}
static int msm_startup(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
unsigned int data, rfr_level;
int ret;
snprintf(msm_port->name, sizeof(msm_port->name),
"msm_serial%d", port->line);
ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
msm_port->name, port);
if (unlikely(ret))
return ret;
msm_init_clock(port);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
/* set automatic RFR level */
data = msm_read(port, UART_MR1);
data &= ~UART_MR1_AUTO_RFR_LEVEL1;
data &= ~UART_MR1_AUTO_RFR_LEVEL0;
data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
msm_write(port, data, UART_MR1);
/* make sure that RXSTALE count is non-zero */
data = msm_read(port, UART_IPR);
if (unlikely(!data)) {
data |= UART_IPR_RXSTALE_LAST;
data |= UART_IPR_STALE_LSB;
msm_write(port, data, UART_IPR);
}
msm_reset(port);
msm_write(port, 0x05, UART_CR); /* enable TX & RX */
/* turn on RX and CTS interrupts */
msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
UART_IMR_CURRENT_CTS;
msm_write(port, msm_port->imr, UART_IMR);
return 0;
}
static int __init msm_console_setup(struct console *co, char *options)
{
struct uart_port *port;
struct msm_port *msm_port;
int baud, flow, bits, parity;
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
msm_port = UART_TO_MSM(port);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
msm_init_clock(port);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
UART_MR2); /* 8N1 */
if (baud < 300 || baud > 115200)
baud = 115200;
msm_set_baud_rate(port, baud);
msm_reset(port);
if (msm_port->is_uartdm) {
msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
msm_write(port, UART_CR_TX_ENABLE, UART_CR);
}
printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static int __init msm_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud, flow, bits, parity;
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
pm_runtime_get_noresume(port->dev);
#ifndef CONFIG_PM_RUNTIME
msm_init_clock(port);
#endif
pm_runtime_resume(port->dev);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
UART_MR2); /* 8N1 */
if (baud < 300 || baud > 115200)
baud = 115200;
msm_set_baud_rate(port, baud);
msm_reset(port);
printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static int __init msm_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud, flow, bits, parity;
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
msm_init_clock(port);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
UART_MR2); /* 8N1 */
if (baud < 300 || baud > 115200)
baud = 115200;
msm_set_baud_rate(port, baud);
msm_reset(port);
/* FIH, Debbie, 2010/01/04 { */
#ifdef CONFIG_FIH_FXX
fih_printk(serial_debug_mask, FIH_DEBUG_ZONE_G0, "msm_serial: console setup on port #%d\n", port->line);
#else
printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
#endif
/* FIH, Debbie, 2010/01/04 } */
return uart_set_options(port, co, baud, parity, bits, flow);
}
static int msm_serial_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct uart_port *port;
port = get_port_from_line(pdev->id);
// BEGIN 0010274: [email protected] 2010-10-27
// Fixed a problem that system don't go to sleep mode.
#if 0 //defined(CONFIG_MACH_LGE_BRYCE)
struct msm_port *msm_port;
if(uart_det_flag){
msm_port = UART_TO_MSM(port);
clk_enable(msm_port->clk);
}
#endif
// END 0010274: [email protected] 2010-10-27
dev_dbg(dev, "pm_runtime: resuming\n");
msm_init_clock(port);
return 0;
}
static int msm_startup(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
unsigned int data, rfr_level;
int ret;
snprintf(msm_port->name, sizeof(msm_port->name),
"msm_serial%d", port->line);
ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
msm_port->name, port);
if (unlikely(ret))
return ret;
#ifndef CONFIG_PM_RUNTIME
msm_init_clock(port);
#endif
pm_runtime_get_sync(port->dev);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
/* set automatic RFR level */
data = msm_read(port, UART_MR1);
data &= ~UART_MR1_AUTO_RFR_LEVEL1;
data &= ~UART_MR1_AUTO_RFR_LEVEL0;
data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
msm_write(port, data, UART_MR1);
/* make sure that RXSTALE count is non-zero */
data = msm_read(port, UART_IPR);
if (unlikely(!data)) {
data |= UART_IPR_RXSTALE_LAST;
data |= UART_IPR_STALE_LSB;
msm_write(port, data, UART_IPR);
}
msm_reset(port);
msm_write(port, 0x05, UART_CR); /* enable TX & RX */
/* turn on RX and CTS interrupts */
msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
UART_IMR_CURRENT_CTS;
msm_write(port, msm_port->imr, UART_IMR);
#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
if (use_low_power_wakeup(msm_port)) {
ret = set_irq_wake(msm_port->wakeup.irq, 1);
if (unlikely(ret))
return ret;
ret = request_irq(msm_port->wakeup.irq, msm_rx_irq,
IRQF_TRIGGER_FALLING,
"msm_serial_wakeup", msm_port);
if (unlikely(ret))
return ret;
disable_irq(msm_port->wakeup.irq);
}
#endif
return 0;
}
static int msm_startup(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
unsigned int data, rfr_level;
int ret;
snprintf(msm_port->name, sizeof(msm_port->name),
"msm_serial%d", port->line);
ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
msm_port->name, port);
if (unlikely(ret))
return ret;
msm_init_clock(port);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
/* set automatic RFR level */
data = msm_read(port, UART_MR1);
data &= ~UART_MR1_AUTO_RFR_LEVEL1;
data &= ~UART_MR1_AUTO_RFR_LEVEL0;
data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
msm_write(port, data, UART_MR1);
/* make sure that RXSTALE count is non-zero */
data = msm_read(port, UART_IPR);
if (unlikely(!data)) {
data |= UART_IPR_RXSTALE_LAST;
data |= UART_IPR_STALE_LSB;
msm_write(port, data, UART_IPR);
}
data = 0;
if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
msm_reset(port);
data = UART_CR_TX_ENABLE;
}
data |= UART_CR_RX_ENABLE;
msm_write(port, data, UART_CR); /* enable TX & RX */
/* Make sure IPR is not 0 to start with*/
if (msm_port->is_uartdm)
msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
/* turn on RX and CTS interrupts */
msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
UART_IMR_CURRENT_CTS;
if (msm_port->is_uartdm) {
msm_write(port, 0xFFFFFF, UARTDM_DMRX);
msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
}
msm_write(port, msm_port->imr, UART_IMR);
return 0;
}
