static int msm_hsphy_init(struct usb_phy *uphy)
{
struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
u32 val;
msm_hsphy_reset(uphy);
/* different sequences based on core version */
phy->core_ver = readl_relaxed(phy->base);
/*
* HSPHY Initialization: Enable UTMI clock and clamp enable HVINTs,
* and disable RETENTION (power-on default is ENABLED)
*/
val = readl_relaxed(phy->base + HS_PHY_CTRL_REG(0));
val |= (USB2_UTMI_CLK_EN | CLAMP_MPM_DPSE_DMSE_EN_N | RETENABLEN);
if (uphy->flags & ENABLE_SECONDARY_PHY) {
val &= ~(USB2_UTMI_CLK_EN | FREECLOCK_SEL);
val |= FREECLK_DIS_WHEN_SUSP;
}
writel_relaxed(val, phy->base + HS_PHY_CTRL_REG(0));
usleep_range(2000, 2200);
if (uphy->flags & ENABLE_SECONDARY_PHY)
msm_usb_write_readback(phy->base, GENERAL_CFG_REG,
SEC_UTMI_FREE_CLK_GFM_SEL1,
SEC_UTMI_FREE_CLK_GFM_SEL1);
if (phy->core_ver >= MSM_CORE_VER_120) {
val = readl_relaxed(phy->base + HS_PHY_CTRL_COMMON_REG);
val |= COMMON_OTGDISABLE0 | COMMON_OTGTUNE0_DEFAULT |
COMMON_COMMONONN | FSEL_DEFAULT | COMMON_RETENABLEN;
if (phy->set_pllbtune) {
val |= COMMON_PLLBTUNE | COMMON_CLKCORE;
val &= ~COMMON_FSEL;
}
writel_relaxed(val, phy->base + HS_PHY_CTRL_COMMON_REG);
}
/*
* write HSPHY init value to QSCRATCH reg to set HSPHY parameters like
* VBUS valid threshold, disconnect valid threshold, DC voltage level,
* preempasis and rise/fall time.
*/
if (override_phy_init)
phy->hsphy_init_seq = override_phy_init;
if (phy->hsphy_init_seq)
msm_usb_write_readback(phy->base,
PARAMETER_OVERRIDE_X_REG(0), 0x03FFFFFF,
phy->hsphy_init_seq & 0x03FFFFFF);
return 0;
}
static int msm_hsphy_notify_connect(struct usb_phy *uphy,
enum usb_device_speed speed)
{
int rc = 0;
struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
phy->cable_connected = true;
if (uphy->flags & PHY_HOST_MODE) {
if (phy->core_ver == MSM_CORE_VER_160 ||
phy->core_ver == MSM_CORE_VER_161) {
/* Some snps usb2 picophy revisions require 3.15 V to
* operate correctly during full speed host mode at
* sub zero temperature.
*/
rc = regulator_set_voltage(phy->vdda33,
USB_HSPHY_3P3_VOL_FSHOST,
USB_HSPHY_3P3_VOL_MAX);
if (rc)
dev_err(phy->phy.dev,
"unable to set voltage for vdda33\n");
}
return 0;
}
if (!(uphy->flags & PHY_VBUS_VALID_OVERRIDE))
return 0;
/* Set External VBUS Valid Select. Set once, can be left on */
if (phy->core_ver >= MSM_CORE_VER_120) {
msm_usb_write_readback(phy->base, HS_PHY_CTRL_COMMON_REG,
COMMON_VBUSVLDEXTSEL0,
COMMON_VBUSVLDEXTSEL0);
} else {
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(0),
VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
}
/* Enable D+ pull-up resistor */
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(0),
VBUSVLDEXT0, VBUSVLDEXT0);
/* Set OTG VBUS Valid from HSPHY to controller */
msm_usb_write_readback(phy->base, HS_PHY_CTRL_REG(0),
UTMI_OTG_VBUS_VALID,
UTMI_OTG_VBUS_VALID);
/* Indicate value is driven by UTMI_OTG_VBUS_VALID bit */
if (phy->core_ver >= MSM_CORE_VER_120)
msm_usb_write_readback(phy->base, HS_PHY_CTRL_REG(0),
SW_SESSVLD_SEL, SW_SESSVLD_SEL);
return 0;
}
static int msm_ssphy_set_suspend(struct usb_phy *uphy, int suspend)
{
struct msm_ssphy *phy = container_of(uphy, struct msm_ssphy, phy);
void __iomem *base = phy->base;
int ret = 0;
if (!!suspend == phy->suspended) {
dev_dbg(uphy->dev, "%s\n", suspend ? "already suspended"
: "already resumed");
return 0;
}
if (suspend) {
/* Clear REF_SS_PHY_EN */
msm_usb_write_readback(base, SS_PHY_CTRL_REG, REF_SS_PHY_EN, 0);
/* Clear REF_USE_PAD */
msm_usb_write_readback(base, SS_PHY_CTRL_REG, REF_USE_PAD, 0);
/* Set TEST_POWERDOWN (enables PHY retention) */
msm_usb_write_readback(base, SS_PHY_CTRL_REG, TEST_POWERDOWN,
TEST_POWERDOWN);
msm_ssusb_ldo_enable(phy, 0);
msm_ssusb_config_vdd(phy, 0);
} else {
msm_ssusb_config_vdd(phy, 1);
msm_ssusb_ldo_enable(phy, 1);
if (phy->phy.flags & ENABLE_SECONDARY_PHY) {
dev_err(uphy->dev, "secondary PHY, skipping reset\n");
goto done;
}
/* Assert SS PHY RESET */
msm_usb_write_readback(base, SS_PHY_CTRL_REG, SS_PHY_RESET,
SS_PHY_RESET);
/* Set REF_USE_PAD */
msm_usb_write_readback(base, SS_PHY_CTRL_REG, REF_USE_PAD,
REF_USE_PAD);
/* Set REF_SS_PHY_EN */
msm_usb_write_readback(base, SS_PHY_CTRL_REG, REF_SS_PHY_EN,
REF_SS_PHY_EN);
/* Clear TEST_POWERDOWN */
msm_usb_write_readback(base, SS_PHY_CTRL_REG, TEST_POWERDOWN,
0);
/* 10usec delay required before de-asserting SS PHY RESET */
udelay(10);
msm_usb_write_readback(base, SS_PHY_CTRL_REG, SS_PHY_RESET, 0);
/*
* Reinitialize SSPHY parameters as SS_PHY RESET will reset
* the internal registers to default values.
*/
msm_ssphy_set_params(uphy);
}
done:
phy->suspended = !!suspend; /* double-NOT coerces to bool value */
return ret;
}
static int msm_hsphy_set_params(struct usb_phy *uphy)
{
struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
bool host = uphy->flags & PHY_HOST_MODE;
int hsphy_init_seq;
/*
* write HSPHY init value to QSCRATCH reg to set HSPHY parameters like
* VBUS valid threshold, disconnect valid threshold, DC voltage level,
* preempasis and rise/fall time.
*/
if (host) {
if (override_phy_init_host)
phy->hsphy_init_seq_host = override_phy_init_host;
hsphy_init_seq = phy->hsphy_init_seq_host;
} else {
if (override_phy_init)
phy->hsphy_init_seq = override_phy_init;
hsphy_init_seq = phy->hsphy_init_seq;
}
if (!hsphy_init_seq)
return 0;
dev_info(uphy->dev, "set phy param for %s value=0x%08x\n",
host ? "host" : "peripheral",
hsphy_init_seq & 0x03FFFFFF);
msm_usb_write_readback(phy->base,
PARAMETER_OVERRIDE_X_REG(0), 0x03FFFFFF,
hsphy_init_seq & 0x03FFFFFF);
msm_hsphy_param_output(uphy);
return 0;
}
static int msm_hsphy_notify_disconnect(struct usb_phy *uphy,
enum usb_device_speed speed)
{
int rc = 0;
struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
phy->cable_connected = false;
if (uphy->flags & PHY_HOST_MODE) {
if (phy->core_ver == MSM_CORE_VER_160 ||
phy->core_ver == MSM_CORE_VER_161) {
rc = regulator_set_voltage(phy->vdda33,
USB_HSPHY_3P3_VOL_MIN,
USB_HSPHY_3P3_VOL_MAX);
if (rc)
dev_err(phy->phy.dev,
"unable to set voltage for vdda33\n");
}
return 0;
}
if (!(uphy->flags & PHY_VBUS_VALID_OVERRIDE))
return 0;
/* Clear OTG VBUS Valid to Controller */
msm_usb_write_readback(phy->base, HS_PHY_CTRL_REG(0),
UTMI_OTG_VBUS_VALID, 0);
/* Disable D+ pull-up resistor */
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(0), VBUSVLDEXT0, 0);
/* Indicate value is no longer driven by UTMI_OTG_VBUS_VALID bit */
if (phy->core_ver >= MSM_CORE_VER_120)
msm_usb_write_readback(phy->base, HS_PHY_CTRL_REG(0),
SW_SESSVLD_SEL, 0);
return 0;
}
static int msm_ssphy_notify_disconnect(struct usb_phy *uphy,
enum usb_device_speed speed)
{
struct msm_ssphy *phy = container_of(uphy, struct msm_ssphy, phy);
if (uphy->flags & PHY_HOST_MODE)
return 0;
if (uphy->flags & PHY_VBUS_VALID_OVERRIDE)
/* Clear power indication to SS phy */
msm_usb_write_readback(phy->base, SS_PHY_CTRL_REG,
LANE0_PWR_PRESENT, 0);
return 0;
}
static int msm_hsphy_init(struct usb_phy *uphy)
{
struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
u32 val;
msm_hsphy_reset(uphy);
/* different sequences based on core version */
phy->core_ver = readl_relaxed(phy->base);
/*
* HSPHY Initialization: Enable UTMI clock and clamp enable HVINTs,
* and disable RETENTION (power-on default is ENABLED)
*/
val = readl_relaxed(phy->base + HS_PHY_CTRL_REG(0));
val |= (USB2_UTMI_CLK_EN | CLAMP_MPM_DPSE_DMSE_EN_N | RETENABLEN);
if (uphy->flags & ENABLE_SECONDARY_PHY) {
val &= ~(USB2_UTMI_CLK_EN | FREECLOCK_SEL);
val |= FREECLK_DIS_WHEN_SUSP;
}
writel_relaxed(val, phy->base + HS_PHY_CTRL_REG(0));
usleep_range(2000, 2200);
if (uphy->flags & ENABLE_SECONDARY_PHY)
msm_usb_write_readback(phy->base, GENERAL_CFG_REG,
SEC_UTMI_FREE_CLK_GFM_SEL1,
SEC_UTMI_FREE_CLK_GFM_SEL1);
if (phy->core_ver >= MSM_CORE_VER_120) {
val = readl_relaxed(phy->base + HS_PHY_CTRL_COMMON_REG);
val |= COMMON_OTGDISABLE0 | COMMON_OTGTUNE0_DEFAULT |
COMMON_COMMONONN | FSEL_DEFAULT | COMMON_RETENABLEN;
if (phy->set_pllbtune) {
val |= COMMON_PLLBTUNE | COMMON_CLKCORE;
val &= ~COMMON_FSEL;
}
writel_relaxed(val, phy->base + HS_PHY_CTRL_COMMON_REG);
}
msm_hsphy_set_params(uphy);
return 0;
}
/*
* write HSPHY init value to QSCRATCH reg to set HSPHY
* parameters like VBUS valid threshold, disconnect valid
* threshold, DC voltage level,preempasis and rise/fall time
*/
static int msm_hsphy_set_params(struct usb_phy *uphy)
{
struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
bool host = uphy->flags & PHY_HOST_MODE;
int seq = 0;
if (override_phy_init) {
seq = override_phy_init;
} else if (host && phy->hsphy_host_init_seq) {
seq = phy->hsphy_host_init_seq;
} else {
seq = phy->hsphy_init_seq;
}
if (seq) {
dev_dbg(uphy->dev, "set param to = 0x%x\n", seq);
msm_usb_write_readback(phy->base,
PARAMETER_OVERRIDE_X_REG(0),
0x03FFFFFF, seq & 0x03FFFFFF);
}
return 0;
}
static int msm_hsphy_set_suspend(struct usb_phy *uphy, int suspend)
{
struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
bool host = uphy->flags & PHY_HOST_MODE;
bool chg_connected = uphy->flags & PHY_CHARGER_CONNECTED;
int i, count;
if (!!suspend == phy->suspended) {
dev_dbg(uphy->dev, "%s\n", suspend ? "already suspended"
: "already resumed");
return 0;
}
if (suspend) {
for (i = 0; i < phy->num_ports; i++) {
/* Clear interrupt latch register */
writel_relaxed(ALT_INTERRUPT_MASK,
phy->base + HS_PHY_IRQ_STAT_REG(i));
/* Enable DP and DM HV interrupts */
if (phy->core_ver >= MSM_CORE_VER_120)
msm_usb_write_readback(phy->base,
ALT_INTERRUPT_EN_REG(i),
(LINESTATE_INTEN |
DPINTEN | DMINTEN),
(LINESTATE_INTEN |
DPINTEN | DMINTEN));
else
msm_usb_write_readback(phy->base,
ALT_INTERRUPT_EN_REG(i),
DPDMHV_INT_MASK,
DPDMHV_INT_MASK);
if (!host) {
/* set the following:
* OTGDISABLE0=1
* USB2_SUSPEND_N_SEL=1, USB2_SUSPEND_N=0
*/
if (phy->core_ver >= MSM_CORE_VER_120)
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_COMMON_REG,
COMMON_OTGDISABLE0,
COMMON_OTGDISABLE0);
else
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(i),
OTGDISABLE0, OTGDISABLE0);
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(i),
(USB2_SUSPEND_N_SEL | USB2_SUSPEND_N),
USB2_SUSPEND_N_SEL);
}
if (!phy->ext_vbus_id)
/* Enable PHY-based IDHV and
*OTGSESSVLD HV interrupts
*/
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(i),
(OTGSESSVLDHV_INTEN | IDHV_INTEN),
(OTGSESSVLDHV_INTEN | IDHV_INTEN));
}
/* Enable PHY retention */
if (!host && !chg_connected) {
if (phy->core_ver == MSM_CORE_VER_120 &&
phy->set_pllbtune)
/*
* On this particular revision the PLLITUNE[1]
* bit acts as the control for the RETENABLEN
* PHY signal.
*/
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_COMMON_REG,
COMMON_PLLITUNE_1, COMMON_PLLITUNE_1);
else if (phy->core_ver >= MSM_CORE_VER_120)
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_COMMON_REG,
COMMON_RETENABLEN, 0);
else
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(0),
RETENABLEN, 0);
if (phy->csr) {
/* switch PHY control to USB2PHY CSRs */
msm_usb_write_readback(phy->csr,
USB2PHY_USB_PHY_CFG0,
USB2PHY_OVERRIDE_EN,
USB2PHY_OVERRIDE_EN);
/* clear suspend_n */
msm_usb_write_readback(phy->csr,
USB2PHY_HS_PHY_CTRL2,
USB2PHY_SUSPEND_N_SEL |
USB2PHY_SUSPEND_N,
USB2PHY_SUSPEND_N_SEL);
/* enable retention */
msm_usb_write_readback(phy->csr,
USB2PHY_HS_PHY_CTRL_COMMON0,
USB2PHY_COMMONONN |
USB2PHY_RETENABLEN, 0);
/* disable internal ref clock buffer */
msm_usb_write_readback(phy->csr,
USB2PHY_USB_PHY_REFCLK_CTRL,
REFCLK_RXTAP_EN, 0);
/* power down PHY */
msm_usb_write_readback(phy->csr,
USB2PHY_USB_PHY_PWRDOWN_CTRL,
PWRDN_B, 0);
}
phy->lpm_flags |= PHY_RETENTIONED;
}
/* can turn off regulators if disconnected in device mode */
if (phy->lpm_flags & PHY_RETENTIONED && !phy->cable_connected) {
if (phy->ext_vbus_id) {
msm_hsusb_ldo_enable(phy, 0);
phy->lpm_flags |= PHY_PWR_COLLAPSED;
}
msm_hsusb_config_vdd(phy, 0);
}
count = atomic_dec_return(&hsphy_active_count);
if (count < 0) {
dev_WARN(uphy->dev, "hsphy_active_count=%d, something wrong?\n",
count);
atomic_set(&hsphy_active_count, 0);
}
} else {
atomic_inc(&hsphy_active_count);
if (phy->lpm_flags & PHY_RETENTIONED && !phy->cable_connected) {
msm_hsusb_config_vdd(phy, 1);
if (phy->ext_vbus_id) {
msm_hsusb_ldo_enable(phy, 1);
phy->lpm_flags &= ~PHY_PWR_COLLAPSED;
}
if (phy->csr) {
/* power on PHY */
msm_usb_write_readback(phy->csr,
USB2PHY_USB_PHY_PWRDOWN_CTRL,
PWRDN_B, PWRDN_B);
/* enable internal ref clock buffer */
msm_usb_write_readback(phy->csr,
USB2PHY_USB_PHY_REFCLK_CTRL,
REFCLK_RXTAP_EN,
REFCLK_RXTAP_EN);
/* disable retention */
msm_usb_write_readback(phy->csr,
USB2PHY_HS_PHY_CTRL_COMMON0,
USB2PHY_COMMONONN |
USB2PHY_RETENABLEN,
USB2PHY_COMMONONN |
USB2PHY_RETENABLEN);
/* switch suspend_n_sel back to HW */
msm_usb_write_readback(phy->csr,
USB2PHY_HS_PHY_CTRL2,
USB2PHY_SUSPEND_N_SEL |
USB2PHY_SUSPEND_N, 0);
msm_usb_write_readback(phy->csr,
USB2PHY_USB_PHY_CFG0,
USB2PHY_OVERRIDE_EN, 0);
}
/* Disable PHY retention */
if (phy->core_ver == MSM_CORE_VER_120 &&
phy->set_pllbtune)
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_COMMON_REG,
COMMON_PLLITUNE_1, 0);
else if (phy->core_ver >= MSM_CORE_VER_120)
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_COMMON_REG,
COMMON_RETENABLEN, COMMON_RETENABLEN);
else
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(0),
RETENABLEN, RETENABLEN);
phy->lpm_flags &= ~PHY_RETENTIONED;
}
if (phy->core_ver >= MSM_CORE_VER_120) {
if (phy->set_pllbtune) {
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_COMMON_REG,
FSEL_MASK, 0);
} else {
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_COMMON_REG,
FSEL_MASK, FSEL_DEFAULT);
}
}
for (i = 0; i < phy->num_ports; i++) {
if (!phy->ext_vbus_id)
/* Disable HV interrupts */
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(i),
(OTGSESSVLDHV_INTEN | IDHV_INTEN),
0);
/* Clear interrupt latch register */
writel_relaxed(ALT_INTERRUPT_MASK,
phy->base + HS_PHY_IRQ_STAT_REG(i));
/* Disable DP and DM HV interrupt */
if (phy->core_ver >= MSM_CORE_VER_120)
msm_usb_write_readback(phy->base,
ALT_INTERRUPT_EN_REG(i),
LINESTATE_INTEN, 0);
else
msm_usb_write_readback(phy->base,
ALT_INTERRUPT_EN_REG(i),
DPDMHV_INT_MASK, 0);
if (!host) {
/* Bring PHY out of suspend */
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(i),
USB2_SUSPEND_N_SEL, 0);
if (phy->core_ver >= MSM_CORE_VER_120)
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_COMMON_REG,
COMMON_OTGDISABLE0,
0);
else
msm_usb_write_readback(phy->base,
HS_PHY_CTRL_REG(i),
OTGDISABLE0, 0);
}
}
/*
* write HSPHY init value to QSCRATCH reg to set HSPHY
* parameters like VBUS valid threshold, disconnect valid
* threshold, DC voltage level,preempasis and rise/fall time
*/
dev_dbg(uphy->dev, "%s set params\n", __func__);
msm_hsphy_set_params(uphy);
}
phy->suspended = !!suspend; /* double-NOT coerces to bool value */
return 0;
}
static int msm_ssphy_set_params(struct usb_phy *uphy)
{
struct msm_ssphy *phy = container_of(uphy, struct msm_ssphy, phy);
u32 data = 0;
/*
* WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
* in HS mode instead of SS mode. Workaround it by asserting
* LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
*/
data = msm_ssusb_read_phycreg(phy->base, 0x102D);
data |= (1 << 7);
msm_ssusb_write_phycreg(phy->base, 0x102D, data);
data = msm_ssusb_read_phycreg(phy->base, 0x1010);
data &= ~0xFF0;
data |= 0x20;
msm_ssusb_write_phycreg(phy->base, 0x1010, data);
/*
* Fix RX Equalization setting as follows
* LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
* LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
* LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
* LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
*/
data = msm_ssusb_read_phycreg(phy->base, 0x1006);
data &= ~(1 << 6);
data |= (1 << 7);
data &= ~(0x7 << 8);
data |= (0x3 << 8);
data |= (0x1 << 11);
msm_ssusb_write_phycreg(phy->base, 0x1006, data);
/*
* Set EQ and TX launch amplitudes as follows
* LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
* LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
* LANE0.TX_OVRD_DRV_LO.EN set to 1.
*/
data = msm_ssusb_read_phycreg(phy->base, 0x1002);
data &= ~0x3F80;
if (ss_phy_override_deemphasis)
phy->deemphasis_val = ss_phy_override_deemphasis;
if (phy->deemphasis_val)
data |= (phy->deemphasis_val << 7);
else
data |= (0x16 << 7);
data &= ~0x7F;
data |= (0x7F | (1 << 14));
msm_ssusb_write_phycreg(phy->base, 0x1002, data);
/*
* Set the QSCRATCH SS_PHY_PARAM_CTRL1 parameters as follows
* TX_FULL_SWING [26:20] amplitude to 127
* TX_DEEMPH_3_5DB [13:8] to 22
* LOS_BIAS [2:0] to 0x5
*/
msm_usb_write_readback(phy->base, SS_PHY_PARAM_CTRL_1,
0x07f03f07, 0x07f01605);
return 0;
}