static ssize_t boot_show(struct kobject *kobj, struct attribute *a, char *buf)
{
if (!strncmp(a->name, MD_SYSFS_ATTR, strlen(MD_SYSFS_ATTR)) && md_show) {
return md_show(buf);
} else if (!strncmp(a->name, INFO_SYSFS_ATTR, strlen(INFO_SYSFS_ATTR))) {
return sprintf(buf, "%04X%04X%04X%04X %x\n", get_chip_code(), get_chip_hw_subcode(),
get_chip_hw_ver_code(), get_chip_sw_ver_code(),
mt_get_chip_sw_ver());
} else {
return sprintf(buf, "%d\n", g_boot_mode);
}
}
static void spm_set_suspend_pcm_ver(void)
{
if (CHIP_SW_VER_02 <= mt_get_chip_sw_ver())
{
/*E2 Suspend FW*/
__spm_suspend.pcmdesc = &suspend_pcm_ca7;
}
else
{
#if SPM_CTRL_BIG_CPU
__spm_suspend.pcmdesc = &suspend_pcm_ca15;
#else
__spm_suspend.pcmdesc = &suspend_pcm_ca7;
#endif
}
}
static int __init gpt_mod_init(void)
{
create_proc_read_entry("gpt_stat", S_IRUGO, NULL, gpt_stat_read, NULL);
#if 0
#ifndef CONFIG_MT6582_FPGA
printk("GPT: chipver=%d\n", mt_get_chip_sw_ver());
#else
printk("GPT: FPGA2\n" );
#endif
#endif
printk("GPT: iniit\n" );
return 0;
}
static int __init gpt_mod_init(void)
{
struct proc_dir_entry *xgpt_dir = NULL;
xgpt_dir = proc_mkdir("mt_xgpt", NULL);
proc_create("xgpt_stat", S_IRUGO, xgpt_dir, &xgpt_cmd_proc_fops);
#if 0
#ifndef CONFIG_MT6582_FPGA
printk("GPT: chipver=%d\n", mt_get_chip_sw_ver());
#else
printk("GPT: FPGA2\n" );
#endif
#endif
printk("GPT: iniit\n" );
return 0;
}
//caller: clk mgr
static void mt_fh_hal_default_conf(void)
{
FH_MSG_DEBUG("%s",__func__);
#if 1
//freqhopping_config(FH_ARMCA7_PLLID, g_default_freq[FH_ARMCA7_PLLID], false);
//freqhopping_config(FH_ARMCA15_PLLID, g_default_freq[FH_ARMCA15_PLLID], false);
freqhopping_config(FH_MAIN_PLLID, g_default_freq[FH_MAIN_PLLID], true);
freqhopping_config(FH_M_PLLID, g_default_freq[FH_M_PLLID], true);
freqhopping_config(FH_MSDC_PLLID, g_default_freq[FH_MSDC_PLLID], true);
//Turn off MMPLL SSC after CHIP_SW_VER_01
if (CHIP_SW_VER_01 <= mt_get_chip_sw_ver())
freqhopping_config(FH_MM_PLLID, g_default_freq[FH_MM_PLLID], true);
//freqhopping_config(FH_VENC_PLLID, g_default_freq[FH_VENC_PLLID], true);
//freqhopping_config(FH_TVD_PLLID, g_default_freq[FH_TVD_PLLID], true);
//freqhopping_config(FH_VCODEC_PLLID, g_default_freq[FH_VCODEC_PLLID], true);
#endif
}
void mt_idle_init(void)
{
int err = 0;
int i = 0;
CHIP_SW_VER ver=mt_get_chip_sw_ver();
if(CHIP_SW_VER_02<=ver)
{
memcpy(idle_switch,idle_switch_E2,sizeof(idle_switch));
//return;//TODO,for E2 default off arch_idle
}
idle_info("[%s]entry!!\n", __func__);
arm_pm_idle = arch_idle;
err = request_gpt(idle_gpt, GPT_ONE_SHOT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
0, NULL, GPT_NOAUTOEN);
if (err) {
idle_info("[%s]fail to request GPT%d\n", __func__,idle_gpt+1);
}
err = 0;
for(i=0;i<NR_CPUS;i++){
err |= cpu_xgpt_register_timer(i,NULL);
}
if (err) {
idle_info("[%s]fail to request cpuxgpt\n", __func__);
}
err = sysfs_create_file(power_kobj, &idle_state_attr.attr);
err |= sysfs_create_file(power_kobj, &soidle_state_attr.attr);
err |= sysfs_create_file(power_kobj, &mcidle_state_attr.attr);
err |= sysfs_create_file(power_kobj, &dpidle_state_attr.attr);
err |= sysfs_create_file(power_kobj, &slidle_state_attr.attr);
err |= sysfs_create_file(power_kobj, &rgidle_state_attr.attr);
if (err) {
idle_err("[%s]: fail to create sysfs\n", __func__);
}
}
int __init chip_mod_init(void)
{
struct mt_chip_drv *p_drv = get_mt_chip_drv();
pr_debug("CODE = %04x %04x %04x %04x, %04x %04x %04x %04x, %04X %04X\n",
__chip_hw_code(), __chip_hw_subcode(), __chip_hw_ver(),
__chip_sw_ver(), __chip_func_code(), __chip_proj_code(),
__chip_date_code(), __chip_fab_code(), mt_get_chip_hw_ver(), mt_get_chip_sw_ver());
p_drv->info_bit_mask |= CHIP_INFO_BIT(CHIP_INFO_HW_CODE) |
CHIP_INFO_BIT(CHIP_INFO_HW_SUBCODE) |
CHIP_INFO_BIT(CHIP_INFO_HW_VER) |
CHIP_INFO_BIT(CHIP_INFO_SW_VER) | CHIP_INFO_BIT(CHIP_INFO_FUNCTION_CODE);
p_drv->get_chip_info = mt_get_chip_info;
pr_debug("CODE = %08X %p", p_drv->info_bit_mask, p_drv->get_chip_info);
return 0;
}
const bool cmdq_driver_support_wait_and_receive_event_in_same_tick(void)
{
#ifdef CMDQ_USE_LEGACY
const unsigned int code = mt_get_chip_hw_code();
CHIP_SW_VER ver = mt_get_chip_sw_ver();
bool support = false;
if (0x6795 == code) {
support = true;
} else if (CHIP_SW_VER_02 <= ver) {
/* SW V2 */
support = true;
} else if (CHIP_SW_VER_01 <= ver) {
support = false;
}
return support;
#else
return true;
#endif
}
static int __init pftracer_init(void)
{
int i, err;
#if defined(ETR_DRAM)
/* DRAM */
void *buff;
dma_addr_t dma_handle;
buff = dma_alloc_coherent(NULL, ETR_BUFF_SIZE, &dma_handle, GFP_KERNEL);
if (!buff) {
return -ENOMEM;
}
etb_driver_data.etr_virt = (u32)buff;
etb_driver_data.etr_phys = dma_handle;
etb_driver_data.etr_len = ETR_BUFF_SIZE;
etb_driver_data.use_etr = 1;
etb_driver_data.etb_regs = IOMEM(DBGAPB_BASE + 0x13000);
#elif defined(ETR_SRAM)
/* SRAM */
etb_driver_data.etr_virt = (u32)ETR_SRAM_VIRT_BASE;
etb_driver_data.etr_phys = (dma_addr_t)ETR_SRAM_PHYS_BASE;
etb_driver_data.etr_len = ETR_BUFF_SIZE;
etb_driver_data.use_etr = 1;
etb_driver_data.etb_regs = IOMEM(DBGAPB_BASE + 0x13000);
#elif defined(ETB)
/* ETB */
etb_driver_data.use_etr = 0;
etb_driver_data.etb_regs = IOMEM(DBGAPB_BASE + 0x11000);
#else
if (CHIP_SW_VER_01 == mt_get_chip_sw_ver()) {
/* SRAM */
etb_driver_data.etr_virt = (u32)ETR_SRAM_VIRT_BASE;
etb_driver_data.etr_phys = (dma_addr_t)ETR_SRAM_PHYS_BASE;
etb_driver_data.etr_len = ETR_BUFF_SIZE;
etb_driver_data.use_etr = 1;
etb_driver_data.etb_regs = IOMEM(DBGAPB_BASE + 0x13000);
} else {
/* ETB */
etb_driver_data.use_etr = 0;
etb_driver_data.etb_regs = IOMEM(DBGAPB_BASE + 0x11000);
}
#endif
#if 0
/* To fix the ACTLK timing issue */
if (CHIP_SW_VER_01 == mt_get_chip_sw_ver()) {
/* CA15 MCI ATCLK */
writel(readl((volatile unsigned int *)(CA7MCUCFG_BASE + 0x248))|0xC, (volatile unsigned int *)(CA7MCUCFG_BASE + 0x248));
}
#endif
for (i = 0; i < NR_CPUS; i++) {
per_cpu(trace_pwr_down, i) = 0;
etm_driver_data[i].pwr_down = &(per_cpu(trace_pwr_down, i));
}
err = platform_device_register(&(etm_device[0]));
if (err) {
pr_err("Fail to register etm_device 0");
return err;
}
err = platform_device_register(&(etm_device[1]));
if (err) {
pr_err("Fail to register etm_device 1");
return err;
}
err = platform_device_register(&(etm_device[2]));
if (err) {
pr_err("Fail to register etm_device 2");
return err;
}
err = platform_device_register(&(etm_device[3]));
if (err) {
pr_err("Fail to register etm_device 3");
return err;
}
err = platform_device_register(&etb_device);
if (err) {
pr_err("Fail to register etb_device");
return err;
}
register_cpu_notifier(&pftracer_notifier);
return 0;
}
static wake_reason_t spm_output_wake_reason(struct wake_status *wakesta, struct pcm_desc *pcmdesc)
{
wake_reason_t wr;
wr = __spm_output_wake_reason(wakesta, pcmdesc, true);
#if 1
memcpy(&suspend_info[log_wakesta_cnt], wakesta, sizeof(struct wake_status));
suspend_info[log_wakesta_cnt].log_index = log_wakesta_index;
log_wakesta_cnt++;
log_wakesta_index++;
if (10 <= log_wakesta_cnt)
{
log_wakesta_cnt = 0;
spm_snapshot_golden_setting = 0;
}
#if 0
else
{
if (2 != spm_snapshot_golden_setting)
{
if ((0x90100000 == wakesta->event_reg) && (0x140001f == wakesta->debug_flag))
spm_snapshot_golden_setting = 1;
}
}
#endif
if (0xFFFFFFF0 <= log_wakesta_index)
log_wakesta_index = 0;
#endif
spm_crit2("big core = %d, suspend dormant state = %d, chip = %d\n", SPM_CTRL_BIG_CPU, spm_dormant_sta, mt_get_chip_sw_ver());
if (0 != spm_ap_mdsrc_req_cnt)
spm_crit2("warning: spm_ap_mdsrc_req_cnt = %d, r7[ap_mdsrc_req] = 0x%x\n", spm_ap_mdsrc_req_cnt, spm_read(SPM_POWER_ON_VAL1) & (1<<17));
if (wakesta->r12 & WAKE_SRC_EINT)
mt_eint_print_status();
if (wakesta->r12 & WAKE_SRC_CLDMA_MD)
exec_ccci_kern_func_by_md_id(0, ID_GET_MD_WAKEUP_SRC, NULL, 0);
return wr;
}
/*
SMI_LARB0: DISP/MDP(MMSYS)
SMI_LARB1: VDEC
SMI_LARB2: ISP
SMI_LARB3: VENC
SMI_LARB4: MJC
*/
void dcm_enable(unsigned int type)
{
#if 1
dcm_info("[%s]type:0x%08x\n", __func__, type);
mutex_lock(&dcm_lock);
if (type & CPU_DCM) {
dcm_info("[%s][CPU_DCM ]=0x%08x\n", __func__,CPU_DCM);
dcm_clrl (MCUSYS_CONFIG , 0x0F9C0000); //0xF020001C,
dcm_setl (CACHE_CONFIG , 0x00000B00); //0xF0200100,set bit8,bit9,bit11=1,
dcm_clrl (CACHE_CONFIG , 0x00000400); //0xF0200100,clear bit10,
dcm_setl (ARMPLL_CTL , 0x00000010); //0xF0200160,set bit4,
dcm_sta |= CPU_DCM;
}
#if 0 //because in 92 there is no register need to be set in TOPCKGEN
if (type & TOPCKGEN_DCM) {
dcm_info("[%s][TOPCKGEN_DCM]=0x%08x\n", __func__,TOPCKGEN_DCM);
#ifdef DCM_ENABLE_DCM_CFG //AXI bus dcm, don't need to set by KL Tong
//default value are all 0,use default value
dcm_writel(DCM_CFG, 0xFFFFFF7F);//set bit0~bit4=0,bit7=0,bit8~bit14=0,bit15=0????
#endif
dcm_sta |= TOPCKGEN_DCM;
}
#endif
//Infrasys_dcm
if (type & IFR_DCM) {
dcm_info("[%s][IFR_DCM ]=0x%08x\n", __func__,IFR_DCM);
dcm_clrl (CA7_CKDIV1 , 0x0000001F); //0x10001008//5'h0,00xxx: 1/1,
if(CHIP_SW_VER_02 == mt_get_chip_sw_ver()){
dcm_setl (INFRA_TOPCKGEN_DCMCTL , 0x00000001); //0x10001010,set0=1,
dcm_clrl (INFRA_TOPCKGEN_DCMCTL , 0x00000770); //0x10001010,set4,5,6,8,9,10=0
}
else{
dcm_setl (INFRA_TOPCKGEN_DCMCTL , 0x00000771); //0x10001010,set0,4,5,6,8,9,10=1,
}
dcm_setl (INFRA_GLOBALCON_DCMCTL, 0x00000303); //0x10001050//set bit0,bit1,bit8,bit9=1,DCM debouncing counter=0,
dcm_setl (INFRA_GLOBALCON_DCMDBC ,0x01000100); //0xF0001054,set bit8,24=1,
dcm_clrl (INFRA_GLOBALCON_DCMDBC ,0x007F007F); //0xF0001054,clear bit0~6,16~22,
dcm_setl (INFRA_GLOBALCON_DCMFSEL,0x10100000); //0xF0001058,
dcm_clrl (INFRA_GLOBALCON_DCMFSEL,0x0F0F0F07); //0xF0001058,
dcm_clrl (MM_MMU_DCM_DIS , 0x0000007F); //0xF0205050,
dcm_clrl (PERISYS_MMU_DCM_DIS , 0x0000007F); //0xF0214050,
//DRAMC
dcm_setl (channel_A_DRAMC_PD_CTRL, 0xC3000000); //0xF00041DC,
dcm_clrl (channel_A_DRAMC_PD_CTRL, 0x00000008); //0xF00041DC,
dcm_setl (channel_B_DRAMC_PD_CTRL, 0xC3000000); //0xF00111DC,
dcm_clrl (channel_B_DRAMC_PD_CTRL, 0x00000008); //0xF00111DC,
dcm_sta |= IFR_DCM;
}
if (type & PER_DCM) {
dcm_info("[%s][PER_DCM ]=0x%08x\n", __func__,PER_DCM);
dcm_setl (PERI_GLOBALCON_DCMCTL , 0x000000F3); //0xF0003050,set bit0,1,4~7,
dcm_clrl (PERI_GLOBALCON_DCMCTL , 0x00001F00); //0x10003050//clear bit8~12,
dcm_clrl (PERI_GLOBALCON_DCMDBC , 0x0000000F); //0x10003054//clear bit0~3 ,
dcm_setl (PERI_GLOBALCON_DCMDBC , 0x000000F0); //0x10003054//set bit4~7=1 ,
dcm_clrl (PERI_GLOBALCON_DCMFSEL, 0x001F0F07); //0x10003058//clear bit0~bit2,bit8~bit11,bit16~bit20,
//MSDC module
dcm_setl (MSDC0_PATCH_BIT1 , 0x00200000); //0xF12300B4//set bit21=1,
dcm_clrl (MSDC0_PATCH_BIT1 , 0xFF800000); //0xF12300B4//clear bit23~bit31=0,
dcm_setl (MSDC1_PATCH_BIT1 , 0x00200000); //0xF12400B4//set bit21=1,
dcm_clrl (MSDC1_PATCH_BIT1 , 0xFF800000); //0xF12400B4//clear bit23~bit31=0,
dcm_setl (MSDC2_PATCH_BIT1 , 0x00200000); //0xF12500B4//set bit21=1,
dcm_clrl (MSDC2_PATCH_BIT1 , 0xFF800000); //0xF12500B4//clear bit23~bit31=0,
dcm_setl (MSDC3_PATCH_BIT1 , 0x00200000); //0xF12600B4//set bit21=1,
dcm_clrl (MSDC3_PATCH_BIT1 , 0xFF800000); //0xF12600B4//clear bit23~bit31=0,
//USB
dcm_clrl (USB0_DCM , 0x00070000); //0x11200700//clear bit16~bit18=0,
//PMIC
dcm_setl (PMIC_WRAP_DCM_EN , 0x00000001); //0x1000D13C//set bit0=1,
//I2C
dcm_setl (I2C0_I2CREG_HW_CG_EN , 0x00000001); //0xF1007054//set bit0=1,
dcm_setl (I2C1_I2CREG_HW_CG_EN , 0x00000001); //0xF1008054//set bit0=1,
dcm_setl (I2C2_I2CREG_HW_CG_EN , 0x00000001); //0xF1009054//set bit0=1,
dcm_setl (I2C3_I2CREG_HW_CG_EN , 0x00000001); //0xF1010054//set bit0=1,
dcm_setl (I2C4_I2CREG_HW_CG_EN , 0x00000001); //0xF1011054//set bit0=1,
dcm_sta |= PER_DCM;
}
if (type & SMI_DCM) {
dcm_info("[%s][SMI_DCM ]=0x%08x\n", __func__,SMI_DCM);
dcm_writel (SMI_COMMON_SMI_DCM , 0x00000001); //0xF4022300//set bit 0=1,
dcm_sta |= SMI_DCM;
}
if (type & EMI_DCM) {
dcm_info("[%s][EMI_DCM ]=0x%08x\n", __func__,EMI_DCM);
dcm_setl (EMI_CONM , 0x40000000); //0xF0203060,set bit30=1,
dcm_clrl (EMI_CONM , 0xBF000000); //0xF0203060,clear bit31,bit29,bit28,bit27~bit27,
dcm_sta |= EMI_DCM;
}
if (type & DIS_DCM) {
dcm_info("[%s][DIS_DCM ]=0x%08x,subsys_is_on(SYS_DIS)=%d\n", __func__,DIS_DCM,subsys_is_on(SYS_DIS));
if (subsys_is_on(SYS_DIS)) {
dcm_writel (MMSYS_HW_DCM_DIS0 , 0x00000000); //0x14000120,
dcm_writel (MMSYS_HW_DCM_DIS_SET0 , 0x00000000); //0x14000124,
dcm_writel (MMSYS_HW_DCM_DIS_CLR0 , 0xFFFFFFFF); //0x14000128,
dcm_writel (MMSYS_HW_DCM_DIS1 , 0x00000000); //0xF4000130,
dcm_writel (MMSYS_HW_DCM_DIS_SET1 , 0x00000000); //0x14000130,
dcm_writel (MMSYS_HW_DCM_DIS_CLR1 , 0xFFFFFFFF); //0x14000134,
dcm_setl (SMI_LARB0_CON_SET , 0x00000010); //0x14210014//set bit4=1,
dcm_sta |= DIS_DCM;
}
}
if (type & ISP_DCM) { //video encoder : sensor=>ISP=>VENC
dcm_info("[%s][ISP_DCM ]=0x%08x,subsys_is_on(SYS_ISP)=%d,,subsys_is_on(SYS_VEN)=%d\n", __func__,ISP_DCM,subsys_is_on(SYS_ISP),subsys_is_on(SYS_VEN));
if (subsys_is_on(SYS_ISP) && subsys_is_on(SYS_VEN)) {
//dcm_clrl (CTL_RAW_DCM_DIS , 0x03FFFFFF); //0xF5004188,clear bit0~25
dcm_clrl (CTL_RAW_D_DCM_DIS , 0x024EAFE8); //0xF500418C,clear bit0~25
dcm_clrl (CTL_DMA_DCM_DIS , 0x07FFFFFF); //0xF5004190,clear bit0~26
dcm_clrl (CTL_RGB_DCM_DIS , 0x0000007F); //0xF5004194,clear bit0~6
dcm_clrl (CTL_YUV_DCM_DIS , 0x000FFFFF); //0xF5004198,clear bit0~19
dcm_clrl (CTL_TOP_DCM_DIS , 0x0000000F); //0xF500419C,clear bit0~3
dcm_clrl (FDVT_CTRL , 0x0000001F); //0xF500B19C,clear bit25~28
dcm_setl (VENC_CLK_CG_CTRL , 0xFFFFFFFF); //0xF80020FC ,
dcm_setl (VENC_CLK_DCM_CTRL , 0x00000001); //0xF80020F4//set bit0=1,
dcm_clrl (JPGENC_DCM_CTRL , 0x00000001); //0xF8003300//clear bit0=0,
dcm_clrl (JPGDEC_DCM_CTRL , 0x00000001); //0xF8004300//clear bit0=0,
dcm_setl (SMI_LARB2_CON_SET , 0x00000010); //0x15001014//set bit0=1,
dcm_setl (SMI_LARB3_CON_SET , 0x00000010); //0x18001014//set bit0=1,
dcm_sta |= ISP_DCM;
}
}
if (type & VDE_DCM) {
dcm_info("[%s][VDE_DCM ]=0x%08x,subsys_is_on(SYS_VDE)=%d\n", __func__,VDE_DCM,subsys_is_on(SYS_VDE));
if (subsys_is_on(SYS_VDE)) {
dcm_clrl (VDEC_DCM_CON , 0x00000001); //0xF6000018,
dcm_setl (SMI_LARB1_CON_SET , 0x00000010); //0xF6010014,set bit4=1,
dcm_sta |= VDE_DCM;
}
}
if (type & MJC_DCM) { //improve video record resloution
if (subsys_is_on(SYS_MJC)) {
dcm_writel (MJC_HW_DCM_DIS , 0x00000000); //0x17000010,
dcm_writel (MJC_HW_DCM_DIS_SET , 0x00000000); //0x17000014,
dcm_writel (MJC_HW_DCM_DIS_CLR , 0x00000000); //0x17000018,
dcm_setl (SMI_LARB4_CON_SET , 0x00000010); //0x17002014//set bit0=1,
dcm_sta |= MJC_DCM;
}
}
mutex_unlock(&dcm_lock);
#endif
}
void mtk_xhci_ck_timer_init(struct xhci_hcd *xhci)
{
void __iomem *addr;
u32 temp = 0;
int num_u3_port;
unsigned int hw_code = mt_get_chip_hw_code();
CHIP_SW_VER sw_code = mt_get_chip_sw_ver();
mtk_xhci_mtk_log("hw code(0x%x), sw_code(0x%x)\n", hw_code, sw_code);
if (0x6595 == hw_code) {
/* The sys125_ck = 1/2 sys_ck = 62.5MHz */
addr = (void __iomem *)_SSUSB_SYS_CK_CTRL(xhci->sif_regs);
temp = readl(addr);
temp |= SSUSB_SYS_CK_DIV2_EN;
writel(temp, addr);
mtk_xhci_mtk_log("mu3d sys_clk, addr 0x%p, value 0x%x\n",
(void *)_SSUSB_SYS_CK_CTRL(xhci->sif_regs), readl((__u32 __iomem *)_SSUSB_SYS_CK_CTRL(xhci->sif_regs)));
num_u3_port = SSUSB_U3_PORT_NUM(readl((void __iomem *)_SSUSB_IP_CAP(xhci->sif_regs)));
if (num_u3_port) {
#if 0
//set MAC reference clock speed
addr = (void __iomem *) (_SSUSB_U3_MAC_BASE(xhci->base_regs) + U3_UX_EXIT_LFPS_TIMING_PAR);
temp = readl(addr);
temp &= ~(0xff << U3_RX_UX_EXIT_LFPS_REF_OFFSET);
temp |= (U3_RX_UX_EXIT_LFPS_REF << U3_RX_UX_EXIT_LFPS_REF_OFFSET);
writel(temp, addr);
addr = (void __iomem *)(_SSUSB_U3_MAC_BASE(xhci->base_regs) + U3_REF_CK_PAR);
temp = readl(addr);
temp &= ~(0xff);
temp |= U3_REF_CK_VAL;
writel(temp, addr);
#endif
/* set U3 MAC SYS_CK */
addr = (void __iomem *)(_SSUSB_U3_SYS_BASE(xhci->base_regs) + U3_TIMING_PULSE_CTRL);
temp = readl(addr);
temp &= ~(0xff);
temp |= MTK_CNT_1US_VALUE;
writel(temp, addr);
}
/* set U2 MAC SYS_CK */
addr = (void __iomem *)(_SSUSB_U2_SYS_BASE(xhci->base_regs) + USB20_TIMING_PARAMETER);
temp &= ~(0xff);
temp |= MTK_TIME_VALUE_1US;
writel(temp, addr);
mtk_xhci_mtk_log("mu3d u2 mac sys_clk, addr 0x%p, value 0x%x\n",
(void *)(_SSUSB_U2_SYS_BASE(xhci->base_regs) + USB20_TIMING_PARAMETER),
readl((void __iomem *)(_SSUSB_U2_SYS_BASE(xhci->base_regs) + (unsigned long)USB20_TIMING_PARAMETER)));
#if 0
if (num_u3_port) {
//set LINK_PM_TIMER=3
addr = (void __iomem *)(_SSUSB_U3_SYS_BASE(xhci->base_regs) + LINK_PM_TIMER);
temp = readl(addr);
temp &= ~(0xf);
temp |= MTK_PM_LC_TIMEOUT_VALUE;
writel(temp, addr);
}
#endif
}
}
