void c2k_modem_reset_platform(void)
{
int ret = 0;
if (infra_ao_base == 0)
c2k_hw_info_init();
c2k_write32(toprgu_base, TOP_RGU_WDT_SWSYSRST,
(c2k_read32(toprgu_base, TOP_RGU_WDT_SWSYSRST) | 0x88000000)
| (0x1 << 15));
#if defined(CONFIG_MTK_LEGACY)
ret = md_power_on(SYS_MD2);
#else
ret = clk_prepare_enable(clk_scp_sys_md2_main);
#endif
pr_debug("[C2K] md_power_on %d\n", ret);
/*step 1: reset C2K */
#if 0
pr_debug("[C2K] set toprgu wdt");
c2k_write32(toprgu_base, TOP_RGU_WDT_SWSYSRST,
(c2k_read32(toprgu_base, TOP_RGU_WDT_SWSYSRST) | 0x88000000)
& (~(0x1 << 15)));
#else
mtk_wdt_set_c2k_sysrst(1);
#endif
pr_debug("[C2K] TOP_RGU_WDT_SWSYSRST = 0x%x\n",
c2k_read32(toprgu_base, TOP_RGU_WDT_SWSYSRST));
/*step 2: wake up C2K */
c2k_write32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL,
c2k_read32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL) | 0x1);
while (!((c2k_read32(infra_ao_base, INFRA_AO_C2K_STATUS) >> 1) & 0x1))
;
c2k_write32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL,
c2k_read32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL) & (~0x1));
pr_debug("[C2K] C2K_SPM_CTRL = 0x%x\n",
c2k_read32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL));
#if 0
while (c2k_read32(c2k_chip_id_base, 0) != 0x020AC000) {
pr_debug("[C2K] C2K_CHIP_ID = 0x%x\n",
c2k_read32(c2k_chip_id_base, 0));
}
pr_debug("[C2K] C2K_CHIP_ID = 0x%x\n", c2k_read32(c2k_chip_id_base, 0));
#endif
}
/*need modify according to dummy ap*/
int md_ccif_let_md_go(struct ccci_modem *md)
{
struct md_ccif_ctrl *md_ctrl = (struct md_ccif_ctrl *)md->private_data;
if (MD_IN_DEBUG(md)) {
CCCI_INF_MSG(md->index, TAG, "DBG_FLAG_JTAG is set\n");
return -1;
}
CCCI_INF_MSG(md->index, TAG, "md_ccif_let_md_go\n");
switch (md->index) {
case MD_SYS2:
/*set the start address to let modem to run */
/*make boot vector programmable */
ccif_write32(md_ctrl->md_boot_slave_Key, 0, MD2_BOOT_VECTOR_KEY_VALUE);
/*after remap, MD ROM address is 0 from MD's view */
ccif_write32(md_ctrl->md_boot_slave_Vector, 0, MD2_BOOT_VECTOR_VALUE);
/*make boot vector take effect */
ccif_write32(md_ctrl->md_boot_slave_En, 0, MD2_BOOT_VECTOR_EN_VALUE);
break;
case MD_SYS3:
/*check if meta mode */
if (is_meta_mode() || get_boot_mode() == FACTORY_BOOT) {
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG,
(ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG) | ETS_SEL_BIT));
}
/*step 1: set C2K boot mode */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG,
(ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG) & (~(0x7 << 8))) | (0x5 <<
8));
CCCI_INF_MSG(md->index, TAG, "C2K_CONFIG = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG));
/*step 2: config srcclkena selection mask */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) & (~(0x3 <<
4)));
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) | (0x2 << 4));
CCCI_INF_MSG(md->index, TAG, "C2K_SPM_CTRL = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | 0xc);
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) & (~(0x1 << 14)));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | (0x1 << 12));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | (0x1 << 27));
CCCI_INF_MSG(md->index, TAG, "SLEEP_CLK_CON = 0x%x\n",
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON));
/*step 3: PMIC VTCXO_1 enable */
pmic_config_interface(0x0A02, 0xA12E, 0xFFFF, 0x0);
/*step 4: reset C2K */
#if 0
ccif_write32(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST,
(ccif_read32
(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST) | 0x88000000) & (~(0x1 <<
15)));
#else
mtk_wdt_set_c2k_sysrst(1);
#endif
CCCI_INF_MSG(md->index, TAG,
"[C2K] TOP_RGU_WDT_SWSYSRST = 0x%x\n",
ccif_read32(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST));
/*step 5: mpu already set */
/*step 6: wake up C2K */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) | 0x1);
while (!
((ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_STATUS) >> 1) & 0x1)) {
CCCI_INF_MSG(md->index, TAG,
"[C2K] C2K_STATUS = 0x%x\n",
ccif_read32(md_ctrl->hw_info->
infra_ao_base,
INFRA_AO_C2K_STATUS));
}
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) & (~0x1));
CCCI_INF_MSG(md->index, TAG,
"[C2K] C2K_SPM_CTRL = 0x%x, C2K_STATUS = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL),
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_STATUS));
break;
}
return 0;
}
void c2k_modem_power_on_platform(void)
{
int ret;
#if ENABLE_C2K_JTAG
/*ARM legacy JTAG for C2K*/
md_gpio_set(0x80000000 | GPIO82, GPIO_MODE_05, GPIO_DIR_IN,
GPIO_OUT_UNSUPPORTED, GPIO_PULL_ENABLE, GPIO_PULL_DOWN,
GPIO_SMT_ENABLE);
md_gpio_set(0x80000000 | GPIO81, GPIO_MODE_05, GPIO_DIR_IN,
GPIO_OUT_UNSUPPORTED, GPIO_PULL_ENABLE, GPIO_PULL_UP,
GPIO_SMT_ENABLE);
md_gpio_set(0x80000000 | GPIO83, GPIO_MODE_05, GPIO_DIR_IN,
GPIO_OUT_UNSUPPORTED, GPIO_PULL_ENABLE, GPIO_PULL_UP,
GPIO_SMT_DISABLE);
md_gpio_set(0x80000000 | GPIO85, GPIO_MODE_05, GPIO_DIR_IN,
GPIO_OUT_UNSUPPORTED, GPIO_PULL_ENABLE, GPIO_PULL_UP,
GPIO_SMT_DISABLE);
md_gpio_set(0x80000000 | GPIO84, GPIO_MODE_05, GPIO_DIR_OUT,
GPIO_OUT_ZERO, GPIO_PULL_EN_UNSUPPORTED,
GPIO_PULL_UNSUPPORTED, GPIO_SMT_UNSUPPORTED);
md_gpio_set(0x80000000 | GPIO86, GPIO_MODE_05, GPIO_DIR_OUT,
GPIO_OUT_ZERO, GPIO_PULL_EN_UNSUPPORTED,
GPIO_PULL_UNSUPPORTED, GPIO_SMT_UNSUPPORTED);
#endif
pr_debug("[C2K] c2k_modem_power_on enter\n");
if (infra_ao_base == 0)
c2k_hw_info_init();
pr_debug("[C2K] prepare to power on c2k\n");
/*step 0: power on MTCMOS */
#if defined(CONFIG_MTK_LEGACY)
ret = md_power_on(SYS_MD2);
#else
ret = clk_prepare_enable(clk_scp_sys_md2_main);
#endif
pr_debug("[C2K] md_power_on %d\n", ret);
/*step 1: set C2K boot mode */
c2k_write32(infra_ao_base, INFRA_AO_C2K_CONFIG,
(c2k_read32(infra_ao_base, INFRA_AO_C2K_CONFIG) &
(~(0x7 << 8))));
pr_debug("[C2K] C2K_CONFIG = 0x%x\n",
c2k_read32(infra_ao_base, INFRA_AO_C2K_CONFIG));
/*step 2: config srcclkena selection mask */
c2k_write32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL,
c2k_read32(infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) & (~(0xF << 2)));
c2k_write32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL,
c2k_read32(infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) | (0x9 << 2));
pr_debug("[C2K] C2K_SPM_CTRL = 0x%x\n",
c2k_read32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL));
c2k_write32(sleep_base, SLEEP_CLK_CON,
c2k_read32(sleep_base, SLEEP_CLK_CON) | 0xc);
c2k_write32(sleep_base, SLEEP_CLK_CON,
c2k_read32(sleep_base, SLEEP_CLK_CON) & (~(0x1 << 14)));
c2k_write32(sleep_base, SLEEP_CLK_CON,
c2k_read32(sleep_base, SLEEP_CLK_CON) | (0x1 << 12));
c2k_write32(sleep_base, SLEEP_CLK_CON,
c2k_read32(sleep_base, SLEEP_CLK_CON) | (0x1 << 27));
pr_debug("[C2K] SLEEP_CLK_CON = 0x%x\n",
c2k_read32(sleep_base, SLEEP_CLK_CON));
/*step 3: PMIC VTCXO_1 enable */
pmic_config_interface(0x0A02, 0xA12E, 0xFFFF, 0x0);
/*step 4: reset C2K */
#if 0
c2k_write32(toprgu_base, TOP_RGU_WDT_SWSYSRST,
(c2k_read32(toprgu_base, TOP_RGU_WDT_SWSYSRST) | 0x88000000)
& (~(0x1 << 15)));
#else
mtk_wdt_set_c2k_sysrst(1);
#endif
pr_debug("[C2K] TOP_RGU_WDT_SWSYSRST = 0x%x\n",
c2k_read32(toprgu_base, TOP_RGU_WDT_SWSYSRST));
/*step 5: set memory remap */
if (first_init) {
first_init = 0;
c2k_write32(infra_ao_base, MD3_BANK0_MAP0,
((((unsigned int)md3_mem_base -
0x40000000) >> 24) | 0x1) & 0xFF);
#if ENABLE_C2K_EMI_PROTECTION
set_c2k_mpu();
#endif
pr_debug("[C2K] MD3_BANK0_MAP0 = 0x%x\n",
c2k_read32(infra_ao_base, MD3_BANK0_MAP0));
}
/*step 6: wake up C2K */
c2k_write32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL,
c2k_read32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL) | 0x1);
while (!((c2k_read32(infra_ao_base, INFRA_AO_C2K_STATUS) >> 1) & 0x1))
;
pr_debug("[C2K] C2K_STATUS = 0x%x\n",
c2k_read32(infra_ao_base, INFRA_AO_C2K_STATUS));
c2k_write32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL,
c2k_read32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL) & (~0x1));
pr_debug("[C2K] C2K_SPM_CTRL = 0x%x, C2K_STATUS = 0x%x\n",
c2k_read32(infra_ao_base, INFRA_AO_C2K_SPM_CTRL),
c2k_read32(infra_ao_base, INFRA_AO_C2K_STATUS));
#if 0
while (c2k_read32(c2k_chip_id_base, 0) != 0x020AC000) {
pr_debug("[C2K] C2K_CHIP_ID = 0x%x\n",
c2k_read32(c2k_chip_id_base, 0));
}
pr_debug("[C2K] C2K_CHIP_ID = 0x%x!!\n",
c2k_read32(c2k_chip_id_base, 0));
#endif
}
