Exemplo n.º 1
0
static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
{
	unsigned long tick_ns;

	if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
		tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
		ndelay(8 * tick_ns);
	}
}
Exemplo n.º 2
0
static void drv_L7_write_data(const unsigned char data)
{
    /* put data on DB1..DB8 */
    drv_generic_parport_data(data);

    /* CS1 = high, RW = low, A0 = high */
    drv_generic_parport_control(SIGNAL_CS1 | SIGNAL_RW | SIGNAL_A0, SIGNAL_CS1 | SIGNAL_A0);

    /* Address Setup Time = 10 ns */
    /* Data Setup Time = 20 ns */
    ndelay(20);

    /* Control L Pulse Width = 22 ns */
    drv_generic_parport_toggle(SIGNAL_CS1, 0, 22);

    /* Address & Data Hold Time = 10 ns */
    ndelay(10);
}
Exemplo n.º 3
0
/*
 * ubicom32sd_send_command_sync
 */
static void ubicom32sd_send_command_sync(struct ubicom32sd_data *ud, u32_t command, u32_t arg)
{
	ud->regs->command = command;
	ud->regs->arg = arg;
	ubicom32_set_interrupt(ud->irq_tx);
	while (ud->regs->command) {
		ndelay(100);
	}
}
/**
 * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
 * @cfg: The cpu frequency settings.
 *
 * Set the divisors from the settings in @cfg, which where generated
 * during the calculation phase by s3c2440_cpufreq_calcdivs().
 */
static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
{
	unsigned long clkdiv, camdiv;

	s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
		     cfg->divs.h_divisor, cfg->divs.p_divisor);

	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	camdiv = __raw_readl(S3C2440_CAMDIVN);

	clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
	camdiv &= ~CAMDIVN_HCLK_HALF;

	switch (cfg->divs.h_divisor) {
	case 1:
		clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
		break;

	case 2:
		clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
		break;

	case 6:
		camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
	case 3:
		clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
		break;

	case 8:
		camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
	case 4:
		clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
		break;

	default:
		BUG();	/* we don't expect to get here. */
	}

	if (cfg->divs.p_divisor != cfg->divs.h_divisor)
		clkdiv |= S3C2440_CLKDIVN_PDIVN;

	/* todo - set pclk. */

	/* Write the divisors first with hclk intentionally halved so that
	 * when we write clkdiv we will under-frequency instead of over. We
	 * then make a short delay and remove the hclk halving if necessary.
	 */

	__raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
	__raw_writel(clkdiv, S3C2410_CLKDIVN);

	ndelay(20);
	__raw_writel(camdiv, S3C2440_CAMDIVN);

	clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
}
Exemplo n.º 5
0
/**************************************************
函数:int io_nrf24l01_init(void)

描述:
    初始化nrf24l01的IO端口 初始化成功返回1
**************************************************/
int io_nrf24l01_init(void)
{
    //方向和上拉
    MISO_UP;             //MISO上拉
    IRQ_UP;
    CE_OUT;
    CSN_OUT;
    SCK_OUT;
    MOSI_OUT;
    MISO_IN;
    IRQ_IN;

    //初始化端口
    udelay(500); 		 //SPI时序延时

    CE_L;
    ndelay(60);
    CSN_H;
    ndelay(60);
    SCK_L;
    ndelay(60);
    IRQ_H;
    ndelay(60);

    nrf24l01_setRx();            //Set to Rx mode
    /*
        //24l01寄存器配置复位
        SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH);         // 写本地地址
        SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH);  // 写接收端地址
        SPI_RW_Reg(WRITE_REG + EN_AA, 0x01);                  //  频道0自动 ACK应答允许
        SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01);        //  允许接收地址只有频道0
        SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x0a);         // 自动重发延时等待250us+86us,自动重发10次
        SPI_RW_Reg(WRITE_REG + RF_CH, 40);                        //   设置信道工作为2.4GHZ,选择射频通道0x40,收发必须一致
        SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); //设置接收数据长度,本次设置为4字节
        SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07);            //设置发射速率为1MHZ,发射功率为最大值0dB
        SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f);               // IRQ收发完成中断响应,16位CRC ,主接收

        CE_H;
    i*/
    // mdelay(1000);             //等待配置完成

    return 1;
}
Exemplo n.º 6
0
static void pixcir_reset(struct pixcir_i2c_ts_data *tsdata)
{
	if (!IS_ERR_OR_NULL(tsdata->gpio_reset)) {
		gpiod_set_value_cansleep(tsdata->gpio_reset, 1);
		ndelay(100);	/* datasheet section 1.2.3 says 80ns min. */
		gpiod_set_value_cansleep(tsdata->gpio_reset, 0);
		/* wait for controller ready. 100ms guess. */
		msleep(100);
	}
}
Exemplo n.º 7
0
static inline void rb532_pata_finish_io(struct ata_port *ap)
{
	struct ata_host *ah = ap->host;
	struct rb532_cf_info *info = ah->private_data;

	/* FIXME: Keep previous delay. If this is merely a fence then
	   ata_sff_sync might be sufficient. */
	ata_sff_dma_pause(ap);
	ndelay(RB500_CF_IO_DELAY);
}
Exemplo n.º 8
0
static void sht15_bh_read_data(struct work_struct *work_s)
{
	int i;
	uint16_t val = 0;
	struct sht15_data *data
		= container_of(work_s, struct sht15_data,
			       read_work);
	
	if (gpio_get_value(data->pdata->gpio_data)) {
		
		atomic_set(&data->interrupt_handled, 0);
		enable_irq(gpio_to_irq(data->pdata->gpio_data));
		
		if (gpio_get_value(data->pdata->gpio_data)
		    || atomic_read(&data->interrupt_handled))
			return;
	}
	
	for (i = 0; i < 16; ++i) {
		val <<= 1;
		gpio_set_value(data->pdata->gpio_sck, 1);
		ndelay(SHT15_TSCKH);
		val |= !!gpio_get_value(data->pdata->gpio_data);
		gpio_set_value(data->pdata->gpio_sck, 0);
		ndelay(SHT15_TSCKL);
		if (i == 7)
			sht15_ack(data);
	}
	
	sht15_end_transmission(data);

	switch (data->flag) {
	case SHT15_READING_TEMP:
		data->val_temp = val;
		break;
	case SHT15_READING_HUMID:
		data->val_humid = val;
		break;
	}

	data->flag = SHT15_READING_NOTHING;
	wake_up(&data->wait_queue);
}
Exemplo n.º 9
0
static inline void rb500_pata_finish_io(struct ata_port *ap)
{
	struct ata_host *ah = ap->host;
	struct rb500_cf_info *info = ah->private_data;

	ata_altstatus(ap);
	ndelay(RB500_CF_IO_DELAY);

	set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
}
Exemplo n.º 10
0
static void set_scl(struct fd_dev *fd, int val)
{
	uint32_t reg;

	reg = fd_readl(fd, FD_REG_I2CR) & ~FD_I2CR_SCL_OUT;
	if (val)
		reg |= FD_I2CR_SCL_OUT;
	fd_writel(fd, reg, FD_REG_I2CR);
	ndelay(2000);
}
Exemplo n.º 11
0
int _nand_dma_sync(void)
{	
	//unmask to start dma
	unsigned long data;
	int retry = 1000000; //fixme

	data = GDMA_READ_REG(GDMA_CTRL_REG1(DMA_CHNUM));
	data &= ~( 0x01 << CH_MASK_OFFSET); 
	GDMA_WRITE_REG(GDMA_CTRL_REG1(DMA_CHNUM), data);

#if 0	
#if defined (CONFIG_RALINK_RT3052)
	// sync status
	while(!(GDMA_READ_REG(RALINK_GDMAISTS) & (1<<DMA_CHNUM)) && retry--) {
		ndelay(1);
		// do nothing
	}
	if (!(GDMA_READ_REG(RALINK_GDMAISTS) & (1<<DMA_CHNUM))) {
		return -1;
	}
	GDMA_WRITE_REG(RALINK_GDMAISTS, 1<<DMA_CHNUM);
#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352)
	while(!(GDMA_READ_REG(RALINK_GDMA_DONEINT) & (1<<DMA_CHNUM)) && retry--) {
		ndelay(1);
	}
	if (!(GDMA_READ_REG(RALINK_GDMA_DONEINT) & (1<<DMA_CHNUM))) {
		return -1;
	}
	GDMA_WRITE_REG(RALINK_GDMA_DONEINT, 1<<DMA_CHNUM);
#endif
#endif	
	// frank added
	while(!(GDMA_READ_REG(RALINK_GDMA_DONEINT) & (1<<DMA_CHNUM)) && retry--) {
		ndelay(1);
	}
	if (!(GDMA_READ_REG(RALINK_GDMA_DONEINT) & (1<<DMA_CHNUM))) {
		return -1;
	}
	GDMA_WRITE_REG(RALINK_GDMA_DONEINT, 1<<DMA_CHNUM);

	return 0;
}
Exemplo n.º 12
0
ide_startstop_t do_rw_taskfile (ide_drive_t *drive, ide_task_t *task)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct ide_taskfile *tf = &task->tf;
	ide_handler_t *handler = NULL;

	if (task->data_phase == TASKFILE_MULTI_IN ||
	    task->data_phase == TASKFILE_MULTI_OUT) {
		if (!drive->mult_count) {
			printk(KERN_ERR "%s: multimode not set!\n",
					drive->name);
			return ide_stopped;
		}
	}

	if (task->tf_flags & IDE_TFLAG_FLAGGED)
		task->tf_flags |= IDE_TFLAG_FLAGGED_SET_IN_FLAGS;

	if ((task->tf_flags & IDE_TFLAG_DMA_PIO_FALLBACK) == 0)
		ide_tf_load(drive, task);

	switch (task->data_phase) {
	case TASKFILE_MULTI_OUT:
	case TASKFILE_OUT:
		hwif->OUTBSYNC(drive, tf->command, IDE_COMMAND_REG);
		ndelay(400);	/* FIXME */
		return pre_task_out_intr(drive, task->rq);
	case TASKFILE_MULTI_IN:
	case TASKFILE_IN:
		handler = task_in_intr;
		/* fall-through */
	case TASKFILE_NO_DATA:
		if (handler == NULL)
			handler = task_no_data_intr;
		/* WIN_{SPECIFY,RESTORE,SETMULT} use custom handlers */
		if (task->tf_flags & IDE_TFLAG_CUSTOM_HANDLER) {
			switch (tf->command) {
			case WIN_SPECIFY: handler = set_geometry_intr;	break;
			case WIN_RESTORE: handler = recal_intr;		break;
			case WIN_SETMULT: handler = set_multmode_intr;	break;
			}
		}
		ide_execute_command(drive, tf->command, handler,
				    WAIT_WORSTCASE, NULL);
		return ide_started;
	default:
		if (task_dma_ok(task) == 0 || drive->using_dma == 0 ||
		    hwif->dma_setup(drive))
			return ide_stopped;
		hwif->dma_exec_cmd(drive, tf->command);
		hwif->dma_start(drive);
		return ide_started;
	}
}
Exemplo n.º 13
0
static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
{
    struct nand_chip *this = mtd->priv;

    omap_writew(0, (OMAP_MPUIO_BASE + OMAP_MPUIO_IO_CNTL));
    omap_writew(byte, this->IO_ADDR_W);
    ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE, 0);
    ndelay(40);
    ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE,
                           AMS_DELTA_LATCH2_NAND_NWE);
}
Exemplo n.º 14
0
static inline void rb153_pata_finish_io(struct ata_port *ap)
{
	struct rb153_cf_info *info = ap->host->private_data;

	/* FIXME: Keep previous delay. If this is merely a fence then
	 * ata_sff_sync might be sufficient. */
	ata_sff_dma_pause(ap);
	ndelay(RB153_CF_IO_DELAY);

	set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
}
Exemplo n.º 15
0
/* CPHA = 0, CPOL = 1 */
static u32_t spi_gpio_bitbang_txrx_mode2(struct spi_gpio_pdata_t * pdat, u32_t val, int bits, int ns)
{
	u32_t oldbit = (!(val & (1 << (bits - 1)))) << 31;

	for(val <<= (32 - bits); bits > 0; bits--)
	{
		if((val & (1 << 31)) != oldbit)
		{
			spi_gpio_setmosi(pdat, val & (1 << 31));
			oldbit = val & (1 << 31);
		}
		ndelay(ns);
		spi_gpio_setsclk(pdat, 0);
		ndelay(ns);
		val <<= 1;
		val |= spi_gpio_getmiso(pdat);
		spi_gpio_setsclk(pdat, 1);
	}
	return val;
}
Exemplo n.º 16
0
/*****************************************************************************
* Function Name : static int tcc_remocon_set_clock_table(int enable);
* Description : remocon clock limit is enable or disable.
* Arguments :
******************************************************************************/
static int tcc_remocon_set_clock_table(int enable)
{
	if(clock_set_enable != enable)
	{
		tcc_cpufreq_set_limit_table(&gtRemoconClockLimitTable, TCC_FREQ_LIMIT_REMOCON, enable);
	}

	clock_set_enable = enable;
	ndelay(1);
	return 0;
}
Exemplo n.º 17
0
static int erst_timedout(u64 *t, u64 spin_unit)
{
	if ((s64)*t < spin_unit) {
		pr_warn(FW_WARN "Firmware does not respond in time.\n");
		return 1;
	}
	*t -= spin_unit;
	ndelay(spin_unit);
	touch_nmi_watchdog();
	return 0;
}
Exemplo n.º 18
0
static void dsi_pll_toggle_lock_detect_8916(
				struct mdss_pll_resources *dsi_pll_res)
{
	/* DSI PLL toggle lock detect setting */
	MDSS_PLL_REG_W(dsi_pll_res->pll_base,
			DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x04);
	ndelay(500);
	MDSS_PLL_REG_W(dsi_pll_res->pll_base,
			DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05);
	udelay(512);
}
int ad7606_reset(struct ad7606_state *st)
{
	if (gpio_is_valid(st->pdata->gpio_reset)) {
		gpio_set_value(st->pdata->gpio_reset, 1);
		ndelay(100); /* t_reset >= 100ns */
		gpio_set_value(st->pdata->gpio_reset, 0);
		return 0;
	}

	return -ENODEV;
}
Exemplo n.º 20
0
static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *io_base = this->priv;

	writew(0, io_base + OMAP_MPUIO_IO_CNTL);
	writew(byte, this->IO_ADDR_W);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
	ndelay(40);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
}
Exemplo n.º 21
0
ide_startstop_t do_rw_taskfile (ide_drive_t *drive, ide_task_t *task)
{
	ide_hwif_t *hwif = drive->hwif;
	struct ide_taskfile *tf = &task->tf;
	ide_handler_t *handler = NULL;
	const struct ide_tp_ops *tp_ops = hwif->tp_ops;
	const struct ide_dma_ops *dma_ops = hwif->dma_ops;

	if (task->data_phase == TASKFILE_MULTI_IN ||
	    task->data_phase == TASKFILE_MULTI_OUT) {
		if (!drive->mult_count) {
			printk(KERN_ERR "%s: multimode not set!\n",
					drive->name);
			return ide_stopped;
		}
	}

	if (task->tf_flags & IDE_TFLAG_FLAGGED)
		task->tf_flags |= IDE_TFLAG_FLAGGED_SET_IN_FLAGS;

	memcpy(&hwif->task, task, sizeof(*task));

	if ((task->tf_flags & IDE_TFLAG_DMA_PIO_FALLBACK) == 0) {
		ide_tf_dump(drive->name, tf);
		tp_ops->set_irq(hwif, 1);
		SELECT_MASK(drive, 0);
		tp_ops->tf_load(drive, task);
	}

	switch (task->data_phase) {
	case TASKFILE_MULTI_OUT:
	case TASKFILE_OUT:
		tp_ops->exec_command(hwif, tf->command);
		ndelay(400);	/* FIXME */
		return pre_task_out_intr(drive, task->rq);
	case TASKFILE_MULTI_IN:
	case TASKFILE_IN:
		handler = task_in_intr;
		/* fall-through */
	case TASKFILE_NO_DATA:
		if (handler == NULL)
			handler = task_no_data_intr;
		ide_execute_command(drive, tf->command, handler,
				    WAIT_WORSTCASE, NULL);
		return ide_started;
	default:
		if ((drive->dev_flags & IDE_DFLAG_USING_DMA) == 0 ||
		    dma_ops->dma_setup(drive))
			return ide_stopped;
		dma_ops->dma_exec_cmd(drive, tf->command);
		dma_ops->dma_start(drive);
		return ide_started;
	}
}
Exemplo n.º 22
0
static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd_to_nand(mtd);
	void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);

	writew(0, io_base + OMAP_MPUIO_IO_CNTL);
	writew(byte, this->IO_ADDR_W);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
	ndelay(40);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
}
static void s3c6410_i2c_stop(int err)
{
    unsigned int i2cstat;
    unsigned long tmp;
	s3c6410_i2c_xfer_data.state = STATE_STOP;
	s3c6410_i2c_xfer_data.err   = err;

	AT24CXX_DBG("STATE_STOP, err = %d\n", err);


	if (s3c6410_i2c_xfer_data.msgs->flags & I2C_M_RD) { /* 读 */
		// 下面两行恢复I2C操作,发出P信号
		//s3c6410_i2c_regs->iicstat = 0x90;
		i2cstat = readl(s3c6410_i2c_xfer_data.regs + S3C2410_IICSTAT);
		i2cstat = S3C2410_IICSTAT_MASTER_RX | S3C2410_IICSTAT_TXRXEN;
        writel(i2cstat, s3c6410_i2c_xfer_data.regs + S3C2410_IICSTAT);

        tmp = readl(s3c6410_i2c_xfer_data.regs + S3C2410_IICCON);
        /* tmp = 0xaf */
        tmp = S3C2410_IICCON_ACKEN | S3C2410_IICCON_TXDIV_16 | S3C2410_IICCON_IRQEN | S3C2410_IICCON_SCALEMASK;  
        writel(tmp, s3c6410_i2c_xfer_data.regs + S3C2410_IICCON);
        //s3c6410_i2c_regs->iiccon  = 0xaf;
		ndelay(50);  // 等待一段时间以便P信号已经发出
	}else { /* 写 */
		// 下面两行用来恢复I2C操作,发出P信号
		i2cstat = readl(s3c6410_i2c_xfer_data.regs + S3C2410_IICSTAT);
		i2cstat = S3C2410_IICSTAT_MASTER_TX | S3C2410_IICSTAT_TXRXEN;
        writel(i2cstat, s3c6410_i2c_xfer_data.regs + S3C2410_IICSTAT);
        //s3c6410_i2c_regs->iicstat = 0xd0;

        tmp = readl(s3c6410_i2c_xfer_data.regs + S3C2410_IICCON);
        /* tmp = 0xaf */
        tmp = S3C2410_IICCON_ACKEN | S3C2410_IICCON_TXDIV_16 | S3C2410_IICCON_IRQEN | S3C2410_IICCON_SCALEMASK;  
        writel(tmp, s3c6410_i2c_xfer_data.regs + S3C2410_IICCON);
        //s3c6410_i2c_regs->iiccon  = 0xaf;
		ndelay(50);  // 等待一段时间以便P信号已经发出
	}

	/* 唤醒 */
	wake_up(&s3c6410_i2c_xfer_data.wait);
}
Exemplo n.º 24
0
static inline int getCTS_gpio(void) {
	int count = 2000;
	while (count-- && !gpio_get_value(GPIO1)){
		ndelay(10);
	}
	if (count <= 0){
		printk(KERN_ALERT "getCTS wrong!!!");
		return 0;
	}
	return 1;

}
Exemplo n.º 25
0
static void dsi_pll_sw_reset_8916(struct mdss_pll_resources *dsi_pll_res)
{
	/*
	 * DSI PLL software reset. Add HW recommended delays after toggling
	 * the software reset bit off and back on.
	 */
	MDSS_PLL_REG_W(dsi_pll_res->pll_base,
			DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
	ndelay(500);
	MDSS_PLL_REG_W(dsi_pll_res->pll_base,
			DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
}
static inline void eeprom_93cx6_pulse_low(struct eeprom_93cx6 *eeprom)
{
	eeprom->reg_data_clock = 0;
	eeprom->register_write(eeprom);

	/*
	 * Add a short delay for the pulse to work.
	 * According to the specifications the "maximum minimum"
	 * time should be 450ns.
	 */
	ndelay(450);
}
Exemplo n.º 27
0
/*
  TODO: sensitivity
*/
void ata2501_init(void)
{
    GPIOD_DIR |= (RESET | STB | SIFMD | (1 << 8) | (1 << 9));
    GPIOD_DIR &= ~SDATA;

    GPIOD &= ~STB;
    GPIOD |= (1 << 8) | SIFMD | (1 << 9);

    GPIOD &= ~RESET;
    ndelay(1000);
    GPIOD |= RESET;
}
Exemplo n.º 28
0
static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *io_base = this->priv;

	writew(0, io_base + OMAP_MPUIO_IO_CNTL);
	writew(byte, this->IO_ADDR_W);
	ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE, 0);
	ndelay(40);
	ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE,
			       AMS_DELTA_LATCH2_NAND_NWE);
}
Exemplo n.º 29
0
static void rb2011_nand_select_chip(int chip_no)
{
	switch (chip_no) {
	case 0:
		gpio_set_value(RB2011_GPIO_NAND_NCE, 0);
		break;
	default:
		gpio_set_value(RB2011_GPIO_NAND_NCE, 1);
		break;
	}
	ndelay(500);
}
Exemplo n.º 30
0
static void write_TM1616(u8 data)
{
	u8 data_temp = data;
	u8 i;
	for(i=0;i<8;i++)
	{
		if((data_temp&0x01)!=0)   //send from lower bit
		{
			DIN_H();
		}
		else
		{
			DIN_L();
		}
		CLK_L();        //TM1616 read data as clk positive edge 
		ndelay(1);
		CLK_H();
		ndelay(1);
		data_temp = data_temp>>1;
	}	
}