void mrf24j40_reset(mrf24j40_t *dev)
{
eui64_t addr_long;
mrf24j40_init(dev);
netdev_ieee802154_reset(&dev->netdev);
/* get an 8-byte unique ID to use as hardware address */
luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN);
addr_long.uint8[0] &= ~(0x01);
addr_long.uint8[0] |= (0x02);
/* set short and long address */
mrf24j40_set_addr_long(dev, ntohll(addr_long.uint64.u64));
mrf24j40_set_addr_short(dev, ntohs(addr_long.uint16[0].u16));
/* set default PAN id */
mrf24j40_set_pan(dev, IEEE802154_DEFAULT_PANID);
mrf24j40_set_chan(dev, IEEE802154_DEFAULT_CHANNEL);
/* configure Immediate Sleep and Wake-Up mode */
mrf24j40_reg_write_short(dev, MRF24J40_REG_WAKECON, MRF24J40_WAKECON_IMMWAKE);
/* set default options */
mrf24j40_set_option(dev, IEEE802154_FCF_PAN_COMP, true);
mrf24j40_set_option(dev, NETDEV_IEEE802154_SRC_MODE_LONG, true);
mrf24j40_set_option(dev, NETDEV_IEEE802154_ACK_REQ, true);
mrf24j40_set_option(dev, MRF24J40_OPT_CSMA, true);
/* go into RX state */
mrf24j40_reset_tasks(dev);
dev->state = 0;
mrf24j40_set_state(dev, MRF24J40_PSEUDO_STATE_IDLE);
DEBUG("mrf24j40_reset(): reset complete.\n");
}
static int _init(netdev_t *netdev)
{
cc2538_rf_t *dev = (cc2538_rf_t *) netdev;
_dev = netdev;
uint16_t pan = cc2538_get_pan();
uint16_t chan = cc2538_get_chan();
uint16_t addr_short = cc2538_get_addr_short();
uint64_t addr_long = cc2538_get_addr_long();
netdev_ieee802154_reset(&dev->netdev);
/* Initialise netdev_ieee802154_t struct */
netdev_ieee802154_set(&dev->netdev, NETOPT_NID,
&pan, sizeof(pan));
netdev_ieee802154_set(&dev->netdev, NETOPT_CHANNEL,
&chan, sizeof(chan));
netdev_ieee802154_set(&dev->netdev, NETOPT_ADDRESS,
&addr_short, sizeof(addr_short));
netdev_ieee802154_set(&dev->netdev, NETOPT_ADDRESS_LONG,
&addr_long, sizeof(addr_long));
cc2538_set_state(dev, NETOPT_STATE_IDLE);
#ifdef MODULE_NETSTATS_L2
memset(&netdev->stats, 0, sizeof(netstats_t));
#endif
return 0;
}
void kw2xrf_reset_phy(kw2xrf_t *dev)
{
netdev_ieee802154_reset(&dev->netdev);
dev->tx_power = KW2XRF_DEFAULT_TX_POWER;
kw2xrf_set_tx_power(dev, dev->tx_power);
kw2xrf_set_channel(dev, KW2XRF_DEFAULT_CHANNEL);
kw2xrf_set_pan(dev, KW2XRF_DEFAULT_PANID);
kw2xrf_set_address(dev);
kw2xrf_set_cca_mode(dev, 1);
kw2xrf_set_rx_watermark(dev, 1);
kw2xrf_set_option(dev, KW2XRF_OPT_AUTOACK, true);
kw2xrf_set_option(dev, KW2XRF_OPT_ACK_REQ, true);
kw2xrf_set_option(dev, KW2XRF_OPT_AUTOCCA, true);
kw2xrf_set_power_mode(dev, KW2XRF_AUTODOZE);
kw2xrf_set_sequence(dev, dev->idle_state);
kw2xrf_clear_dreg_bit(dev, MKW2XDM_PHY_CTRL2, MKW2XDM_PHY_CTRL2_SEQMSK);
kw2xrf_enable_irq_b(dev);
DEBUG("[kw2xrf] init phy and (re)set to channel %d and pan %d.\n",
KW2XRF_DEFAULT_CHANNEL, KW2XRF_DEFAULT_PANID);
}
