bool nextSlot() //Brennan
{
if (currentCol==dim-1)
{
if (currentRow!=dim-1)
{
currentCol=0;
currentRow+=1;
}
else
{
return false;
}
}
else
{
currentCol+=1;
}
if (preassigned[currentRow][currentCol] ==true)
{
return nextSlot();
}
return true;
}
SMPCache::Line * SMPCache::getLineLE(PAddr addr, tls::Epoch * eph)
{
nextSlot();
Line *l= cache->findLine(addr);
if ((l->getEpoch())->getClock() < eph->getClock())
return l;
else return 0;
}
Time_t PortNPipe::occupySlots(int nSlots)
{
// How to optimize this function (ala PortFullyPipe::occupySlots)?
// Can someone do it?
avgTime.sample(portBusyUntil[0]-globalClock);
doStats = false;
Time_t t = nextSlot();
for(int i=1;i<nSlots;i++)
nextSlot();
doStats = true;
return t;
}
void SMPSystemBus::read(MemRequest *mreq)
{
if(pendReqsTable.find(mreq) == pendReqsTable.end()) {
doReadCB::scheduleAbs(nextSlot(mreq)+delay, this, mreq);
} else {
doRead(mreq);
}
}
void SMPSystemBus::write(MemRequest *mreq)
{
SMPMemRequest *sreq = static_cast<SMPMemRequest *>(mreq);
if(pendReqsTable.find(mreq) == pendReqsTable.end()) {
doWriteCB::scheduleAbs(nextSlot(mreq)+delay, this, mreq);
} else {
doWrite(mreq);
}
}
void SMPSystemBus::finalizeAccess(MemRequest *mreq)
{
PAddr addr = mreq->getPAddr();
SMPMemRequest *sreq = static_cast<SMPMemRequest *>(mreq);
pendReqsTable.erase(mreq);
// request completed, respond to requestor
// (may have to come back later to go to memory)
sreq->goUpAbs(nextSlot(mreq)+delay);
}
void SMPCache::write(MemRequest *mreq)
{
PAddr addr = mreq->getPAddr();
if (!outsReq->issue(addr)) {
outsReq->addEntry(addr, doWriteCB::create(this, mreq),
doWriteCB::create(this, mreq));
writeHalfMiss.inc();
return;
}
doWriteCB::scheduleAbs(nextSlot(), this, mreq);
}
SMPCache::Line *SMPCache::allocateLine(PAddr addr, MemRequest *mreq, CallbackBase *cb)
{
PAddr rpl_addr = 0;
I(cache->findLine(addr)==0);
//I(cache->findLineDebug(addr) == 0);
if (cache->findLineDebug(addr))
printf("Error\n");
Line *l = cache->findLine2Replace(addr);
if(!l) {
// need to schedule allocate line for next cycle
doAllocateLineCB::scheduleAbs(globalClock+1, this, addr, 0, mreq,cb);
return 0;
}
rpl_addr = cache->calcAddr4Tag(l->getTag());
lineFill.inc();
nextSlot(); // have to do an access to check which line is free
if(!l->isValid()) {
cb->destroy();
l->setTag(cache->calcTag(addr));
return l;
}
if(isHighestLevel()) {
if(l->isDirty()) {
allocDirty.inc();
//This prevents further acces to this line
//l->changeStateTo(SMP_TRANS_INV_D);
doWriteBack(mreq);
}
cb->destroy();
l->invalidate();
l->setTag(cache->calcTag(addr));
return l;
}
I(pendInvTable.find(rpl_addr) == pendInvTable.end());
pendInvTable[rpl_addr].outsResps = getNumCachesInUpperLevels();
pendInvTable[rpl_addr].cb = doAllocateLineCB::create(this, addr, rpl_addr, mreq,cb);
pendInvTable[rpl_addr].invalidate = false;
protocol->preInvalidate(l);
invUpperLevel(rpl_addr, cache->getLineSize(), this);
return 0;
}
void SMPCache::realInvalidateTLS(PAddr addr, ushort size)
{
//Invalidate without writeback
while(size) {
Line *l = cache->findLine(addr);
if (l) {
nextSlot(); // counts for occupancy to invalidate line
I(l->isValid());
l->invalidate();
}
addr += cache->getLineSize();
size -= cache->getLineSize();
}
}
void initialize() {
//printf("starting initialize\n");
setupPreassigned();
//printf("preassigned set\n");
setupCandidateLists();
//printf("candidate lists set\n");
currentCol = 0;
currentRow = 0;
while (preassigned[currentRow][currentCol]) {
nextSlot();
}
//printf("slot initialized\n");
copyCandidates(currentRow, currentCol);
//printf("candidates copied\n");
initialized = true;
//printf("initialized\n");
}
InfoEventStackWidget::InfoEventStackWidget(QXmppClient *client, QWidget *parent) :
QWidget(parent),
ui(new Ui::InfoEventStackWidget),
m_client(client),
m_timeLine(new QTimeLine(150, this))
{
ui->setupUi(this);
connect(ui->closeButton, SIGNAL(clicked()),
this, SLOT(closeSlot()) );
connect(ui->previousButton, SIGNAL(clicked()),
this, SLOT(previousSlot()) );
connect(ui->nextButton , SIGNAL(clicked()),
this, SLOT(nextSlot()) );
connect(m_timeLine, SIGNAL(valueChanged(qreal)),
this, SLOT(animeSlot(qreal)) );
}
void SMPCache::realInvalidate(PAddr addr, ushort size)
{
while(size) {
Line *l = cache->findLine(addr);
if (l) {
nextSlot(); // counts for occupancy to invalidate line
I(l->isValid());
if (l->isDirty()) {
invalDirty.inc();
doWriteBack(addr);
}
l->invalidate();
}
addr += cache->getLineSize();
size -= cache->getLineSize();
}
}
void SMPCache::doWrite(MemRequest *mreq)
{
PAddr addr = mreq->getPAddr();
Line *l = cache->writeLine(addr);
//LINE exists in cache
#ifdef TLS
if (l && !l->isLocked()) {
if (mreq->isDataReq()==true){
//Check for Epoch match
//If Epoch mismatch -read miss, invalidate line
if (l->getEpoch()!=mreq->getEpoch())
{
l=0;
if(!l && mreq->getMemOperation() == MemWrite) {
mreq->mutateWriteToRead();
}
if (!mutExclBuffer->issue(addr)) {
mutExclBuffer->addEntry(addr, sendWriteCB::create(this, mreq),
sendReadCB::create(this, mreq));
return;
}
invalidateLineTLS(mreq);
mutExclBuffer->retire(addr);
epochMissW.inc();
}
//WRITE HIT-----------------------
else
{
//Broadcast write hit on bus- if If others exposed is set
if (l->getCacheFlags()->getOE())
{
(l->getCacheFlags())->setWordWM(getOffsetInLine(addr));
if(mreq->getMemOperation() == MemWrite) {
mreq->mutateWriteToRead();
}
writeHitProp.inc();//write hit but broadcast
writeHit.inc();//Propagated hits still counted
if (!mutExclBuffer->issue(addr)) {
mutExclBuffer->addEntry(addr, sendWriteCB::create(this, mreq),
sendWriteCB::create(this, mreq));
return;
}
sendWrite(mreq);
return;
}
//Dont broadcast
else
{
writeHit.inc();
outsReq->retire(addr);
(l->getCacheFlags())->setWordWM(getOffsetInLine(addr));
mreq->goUp(hitDelay);
return;
}
}
}
else{
writeHit.inc();
outsReq->retire(addr);
mreq->goUp(hitDelay);
return;
}
}
#else
if (l && l->canBeWritten()) {
writeHit.inc();
outsReq->retire(addr);
mreq->goUp(hitDelay);
return;
}
#endif
//LINE LOCKED RETRY
if (l && l->isLocked()) {
writeRetry.inc();
doWriteCB::scheduleAbs(nextSlot(), this, mreq);
return;
}
GI(l, !l->isLocked());
// this should never happen unless this is highest level because L2
// is inclusive; there is only one case in which this could happen when
// SMPCache is used as an L2:
// 1) line is written in L1 and scheduled to go down to L2
// 2) line is invalidated in both L1 and L2
// 3) doWrite in L2 is executed after line is invalidated
if(!l && mreq->getMemOperation() == MemWrite) {
mreq->mutateWriteToRead();
}
writeMiss.inc();
if (!mutExclBuffer->issue(addr)) {
mutExclBuffer->addEntry(addr, sendWriteCB::create(this, mreq),
sendWriteCB::create(this, mreq));
return;
}
sendWrite(mreq);
}
void SMPSystemBus::push(MemRequest *mreq)
{
doPushCB::scheduleAbs(nextSlot(mreq)+delay, this, mreq);
}
Time_t PortNPipe::nextSlot()
{
return nextSlot(ocp);
}
int firstSlot (void) const { return nextSlot(-1); }
void SMPSystemBus::returnAccess(MemRequest *mreq)
{
mreq->goUpAbs(nextSlot(mreq)+delay);
}
SMPCache::Line *SMPCache::getLine(PAddr addr)
{
nextSlot();
return cache->findLine(addr);
}
void SMPCache::doInvalidateLineTLS(MemRequest *mreq)
{
PAddr addr=mreq->getPAddr();
Line *l = cache->findLine(addr);
ushort size =cache->getLineSize();
I(l);
I(pendInvTable.find(addr) == pendInvTable.end());
pendInvTable[addr].outsResps = getNumCachesInUpperLevels();
pendInvTable[addr].cb = dummyCB::create(this,mreq);;
pendInvTable[addr].invalidate = true;
protocol->preInvalidate(l);
if(!isHighestLevel()) {
invUpperLevel(addr, cache->getLineSize(), this);
return;
}
//doInvalidate(addr, cache->getLineSize());
///Do invalidate
I(pendInvTable.find(addr) != pendInvTable.end());
CallbackBase *cb = 0;
bool invalidate = false;
PendInvTable::iterator it = pendInvTable.find(addr);
Entry *record = &(it->second);
if(--(record->outsResps) <= 0) {
cb = record->cb;
invalidate = record->invalidate;
pendInvTable.erase(addr);
}
if(cb)
EventScheduler::schedule((TimeDelta_t) 2,cb);
//if(invalidate)
//realInvalidate(addr, size);
if(invalidate)
{
while(size) {
//Line *l = cache->findLine(addr);
if (l) {
nextSlot(); // counts for occupancy to invalidate line
I(l->isValid());
if (l->isDirty()) {
invalDirty.inc();
//This prevents further acces to this line
//l->changeStateTo(SMP_TRANS_INV_D);
doWriteBack(mreq);
}
l->invalidate();
}
addr += cache->getLineSize();
size -= cache->getLineSize();
}
}
//mutExclBuffer->retire(addr);
}
// receives requests from other caches
void SMPCache::receiveFromBelow(SMPMemRequest *sreq) {
//TLS error- for writeback miss delay will incur needless delay- FIX
doReceiveFromBelowCB::scheduleAbs(nextSlot() + missDelay, this, sreq);
}
void SMPCache::doRead(MemRequest *mreq)
{
PAddr addr = mreq->getPAddr();
Line *l = cache->readLine(addr);
//Line in Cache
if (l && l->canBeRead()) {
#ifdef TLS
if (mreq->isDataReq()==true){
//Check for Epoch match
//If Epoch mismatch -read miss, invalidate line
if (l->getEpoch()!=mreq->getEpoch())
{
//printf("Line Epoch %d:%d\n",l->getEpoch()->getClock(),l->getEpoch()->getTid());
if (!mutExclBuffer->issue(addr)) {
mutExclBuffer->addEntry(addr, sendReadCB::create(this, mreq),
sendReadCB::create(this, mreq));
return;
}
invalidateLineTLS(mreq);
l=0;
mutExclBuffer->retire(addr);
epochMissR.inc();
}
//READ HIT-----------------------
else
{
//Dont broadcast- if Any word is read exposed or write modify flag for word is set
if (isLineExposedRead(l) || isWordWriteModified(l,addr))
{
readHit.inc();
outsReq->retire(addr);
(l->getCacheFlags())->setWordER(getOffsetInLine(addr));//WM automatically checked
mreq->goUp(hitDelay);
return;
}
//Broadcast read hit on bus
else
{
readHitProp.inc();
readHit.inc();//Propagated hits still counted
(l->getCacheFlags())->setWordER(getOffsetInLine(addr));//WM automatically checked
if (!mutExclBuffer->issue(addr)) {
mutExclBuffer->addEntry(addr, sendReadCB::create(this, mreq),
sendReadCB::create(this, mreq));
return;
}
sendRead(mreq);
return;
}
}
}
else
{
readHit.inc();
outsReq->retire(addr);
mreq->goUp(hitDelay);
return;
}
#else
readHit.inc();
outsReq->retire(addr);
mreq->goUp(hitDelay);
return;
#endif
}
//Read Miss------------------
if (l && l->isLocked()) {
//printf("Being Invalidated\n");
readRetry.inc();
doReadCB::scheduleAbs(nextSlot(), this, mreq);
return;
}
GI(l, !l->isLocked());
readMiss.inc();
if (!mutExclBuffer->issue(addr)) {
mutExclBuffer->addEntry(addr, sendReadCB::create(this, mreq),
sendReadCB::create(this, mreq));
return;
}
sendRead(mreq);
}
