void ddb_local0_irqdispatch(struct pt_regs *regs)
{
u32 mask;
int nile4_irq;
mask = nile4_get_irq_stat(0);
/* Handle the timer interrupt first */
#if 0
if (mask & (1 << NILE4_INT_GPT)) {
do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
mask &= ~(1 << NILE4_INT_GPT);
}
#endif
for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
if (mask & 1) {
if (nile4_irq == NILE4_INT_INTE) {
int i8259_irq;
nile4_clear_irq(NILE4_INT_INTE);
i8259_irq = nile4_i8259_iack();
do_IRQ(i8259_irq, regs);
} else
do_IRQ(nile4_to_irq(nile4_irq), regs);
}
}
static void __init ddb_timer_init(struct irqaction *irq)
{
/* set the clock to 1 Hz */
nile4_out32(NILE4_T2CTRL, 1000000);
/* enable the General-Purpose Timer */
nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
/* reset timer */
nile4_out32(NILE4_T2CNTR, 0);
/* enable interrupt */
setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
change_c0_status(ST0_IM,
IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
}
void ddb_local0_irqdispatch(struct pt_regs *regs)
{
u32 mask;
int nile4_irq;
#if 1
volatile static int nesting = 0;
if (nesting++ == 0)
ddb5074_led_d3(1);
ddb5074_led_hex(nesting < 16 ? nesting : 15);
#endif
mask = nile4_get_irq_stat(0);
nile4_clear_irq_mask(mask);
/* Handle the timer interrupt first */
if (mask & (1 << NILE4_INT_GPT)) {
nile4_disable_irq(NILE4_INT_GPT);
do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
nile4_enable_irq(NILE4_INT_GPT);
mask &= ~(1 << NILE4_INT_GPT);
}
for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
if (mask & 1) {
nile4_disable_irq(nile4_irq);
if (nile4_irq == NILE4_INT_INTE) {
int i8259_irq = nile4_i8259_iack();
i8259_do_irq(i8259_irq, regs);
} else
do_IRQ(nile4_to_irq(nile4_irq), regs);
nile4_enable_irq(nile4_irq);
}
#if 1
if (--nesting == 0)
ddb5074_led_d3(0);
ddb5074_led_hex(nesting < 16 ? nesting : 15);
#endif
}
#define PCI_EXT_INTC 10
#define PCI_EXT_INTD 11
#define PCI_EXT_INTE 12
/*
* based on ddb5477 manual page 11
*/
#define MAX_SLOT_NUM 21
static unsigned char irq_map[MAX_SLOT_NUM] = {
/* SLOT: 0, AD:11 */ 0xff,
/* SLOT: 1, AD:12 */ 0xff,
/* SLOT: 2, AD:13 */ 9, /* USB */
/* SLOT: 3, AD:14 */ 10, /* PMU */
/* SLOT: 4, AD:15 */ 0xff,
/* SLOT: 5, AD:16 */ 0x0, /* P2P bridge */
/* SLOT: 6, AD:17 */ nile4_to_irq(PCI_EXT_INTB),
/* SLOT: 7, AD:18 */ nile4_to_irq(PCI_EXT_INTC),
/* SLOT: 8, AD:19 */ nile4_to_irq(PCI_EXT_INTD),
/* SLOT: 9, AD:20 */ nile4_to_irq(PCI_EXT_INTA),
/* SLOT: 10, AD:21 */ 0xff,
/* SLOT: 11, AD:22 */ 0xff,
/* SLOT: 12, AD:23 */ 0xff,
/* SLOT: 13, AD:24 */ 14, /* HD controller, M5229 */
/* SLOT: 14, AD:25 */ 0xff,
/* SLOT: 15, AD:26 */ 0xff,
/* SLOT: 16, AD:27 */ 0xff,
/* SLOT: 17, AD:28 */ 0xff,
/* SLOT: 18, AD:29 */ 0xff,
/* SLOT: 19, AD:30 */ 0xff,
/* SLOT: 20, AD:31 */ 0xff
};
