void gennor(usf_state_t * state)
{
#ifdef INTERPRET_NOR
gencallinterp(state, (unsigned int)state->current_instruction_table.NOR, 0);
#else
int rs1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rs);
int rs2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rs);
int rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt);
int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt);
int rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd);
int rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd);
if (rt1 != rd1 && rs1 != rd1)
{
mov_reg32_reg32(state, rd1, rs1);
mov_reg32_reg32(state, rd2, rs2);
or_reg32_reg32(state, rd1, rt1);
or_reg32_reg32(state, rd2, rt2);
not_reg32(state, rd1);
not_reg32(state, rd2);
}
else
{
int temp = lru_register(state);
free_register(state, temp);
mov_reg32_reg32(state, temp, rs1);
or_reg32_reg32(state, temp, rt1);
mov_reg32_reg32(state, rd1, temp);
mov_reg32_reg32(state, temp, rs2);
or_reg32_reg32(state, temp, rt2);
mov_reg32_reg32(state, rd2, temp);
not_reg32(state, rd1);
not_reg32(state, rd2);
}
#endif
}
void gennor()
{
#ifdef INTERPRET_NOR
gencallinterp((unsigned long)NOR, 0);
#else
int rs1 = allocate_64_register1((unsigned long *)dst->f.r.rs);
int rs2 = allocate_64_register2((unsigned long *)dst->f.r.rs);
int rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt);
int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt);
int rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd);
int rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd);
if (rt1 != rd1 && rs1 != rd1)
{
mov_reg32_reg32(rd1, rs1);
mov_reg32_reg32(rd2, rs2);
or_reg32_reg32(rd1, rt1);
or_reg32_reg32(rd2, rt2);
not_reg32(rd1);
not_reg32(rd2);
}
else
{
int temp = lru_register();
free_register(temp);
mov_reg32_reg32(temp, rs1);
or_reg32_reg32(temp, rt1);
mov_reg32_reg32(rd1, temp);
mov_reg32_reg32(temp, rs2);
or_reg32_reg32(temp, rt2);
mov_reg32_reg32(rd2, temp);
not_reg32(rd1);
not_reg32(rd2);
}
#endif
}
void gennor(void)
{
#ifdef INTERPRET_NOR
gencallinterp((unsigned int)cached_interpreter_table.NOR, 0);
#else
int rs1 = allocate_64_register1((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs);
int rs2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs);
int rt1 = allocate_64_register1((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt);
int rt2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt);
int rd1 = allocate_64_register1_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd);
int rd2 = allocate_64_register2_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd);
if (rt1 != rd1 && rs1 != rd1)
{
mov_reg32_reg32(rd1, rs1);
mov_reg32_reg32(rd2, rs2);
or_reg32_reg32(rd1, rt1);
or_reg32_reg32(rd2, rt2);
not_reg32(rd1);
not_reg32(rd2);
}
else
{
int temp = lru_register();
free_register(temp);
mov_reg32_reg32(temp, rs1);
or_reg32_reg32(temp, rt1);
mov_reg32_reg32(rd1, temp);
mov_reg32_reg32(temp, rs2);
or_reg32_reg32(temp, rt2);
mov_reg32_reg32(rd2, temp);
not_reg32(rd1);
not_reg32(rd2);
}
#endif
}