Exemplo n.º 1
0
static int
nvd0_disp_base_init(struct nouveau_object *object)
{
	struct nv50_disp_priv *priv = (void *)object->engine;
	struct nv50_disp_base *base = (void *)object;
	int ret, i;
	u32 tmp;

	ret = nouveau_parent_init(&base->base);
	if (ret)
		return ret;

	/* The below segments of code copying values from one register to
	 * another appear to inform EVO of the display capabilities or
	 * something similar.
	 */

	/* ... CRTC caps */
	for (i = 0; i < priv->head.nr; i++) {
		tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
		nv_wr32(priv, 0x6101b4 + (i * 0x800), tmp);
		tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
		nv_wr32(priv, 0x6101b8 + (i * 0x800), tmp);
		tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
		nv_wr32(priv, 0x6101bc + (i * 0x800), tmp);
	}

	/* ... DAC caps */
	for (i = 0; i < priv->dac.nr; i++) {
		tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
		nv_wr32(priv, 0x6101c0 + (i * 0x800), tmp);
	}

	/* ... SOR caps */
	for (i = 0; i < priv->sor.nr; i++) {
		tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
		nv_wr32(priv, 0x6301c4 + (i * 0x800), tmp);
	}

	/* steal display away from vbios, or something like that */
	if (nv_rd32(priv, 0x6100ac) & 0x00000100) {
		nv_wr32(priv, 0x6100ac, 0x00000100);
		nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
		if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
			nv_error(priv, "timeout acquiring display\n");
			return -EBUSY;
		}
	}

	/* point at display engine memory area (hash table, objects) */
	nv_wr32(priv, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9);

	/* enable supervisor interrupts, disable everything else */
	nv_wr32(priv, 0x610090, 0x00000000);
	nv_wr32(priv, 0x6100a0, 0x00000000);
	nv_wr32(priv, 0x6100b0, 0x00000307);

	return 0;
}
Exemplo n.º 2
0
static int
nvd0_disp_base_init(struct nouveau_object *object)
{
    struct nv50_disp_priv *priv = (void *)object->engine;
    struct nv50_disp_base *base = (void *)object;
    int ret, i;
    u32 tmp;

    ret = nouveau_parent_init(&base->base);
    if (ret)
        return ret;

    /* The below segments of code copying values from one register to
     * another appear to inform EVO of the display capabilities or
     * something similar.
     */

    /* ... CRTC caps */
    for (i = 0; i < priv->head.nr; i++) {
        tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
        nv_wr32(priv, 0x6101b4 + (i * 0x800), tmp);
        tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
        nv_wr32(priv, 0x6101b8 + (i * 0x800), tmp);
        tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
        nv_wr32(priv, 0x6101bc + (i * 0x800), tmp);
    }

    /* ... DAC caps */
    for (i = 0; i < priv->dac.nr; i++) {
        tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
        nv_wr32(priv, 0x6101c0 + (i * 0x800), tmp);
    }

    /* ... SOR caps */
    for (i = 0; i < priv->sor.nr; i++) {
        tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
        nv_wr32(priv, 0x6301c4 + (i * 0x800), tmp);
    }

    /* steal display away from vbios, or something like that */
    if (nv_rd32(priv, 0x6100ac) & 0x00000100) {
        nv_wr32(priv, 0x6100ac, 0x00000100);
        nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
        if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
            nv_error(priv, "timeout acquiring display\n");
            return -EBUSY;
        }
    }

    /* point at display engine memory area (hash table, objects) */
    nv_wr32(priv, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9);

    /* enable supervisor interrupts, disable everything else */
    nv_wr32(priv, 0x610090, 0x00000000);
    nv_wr32(priv, 0x6100a0, 0x00000000);
    nv_wr32(priv, 0x6100b0, 0x00000307);

    /* disable underflow reporting, preventing an intermittent issue
     * on some nve4 boards where the production vbios left this
     * setting enabled by default.
     *
     * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
     */
    for (i = 0; i < priv->head.nr; i++)
        nv_mask(priv, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);

    return 0;
}