// --------------------------------------------------------------------------
void nrf24SetTxPipeAddress(BYTE *address, BOOL ack)
{
nrf24_writeRegister(NRF24_REG_TX_ADDR, address, addr_width);
// configure pipe 0 with same address as TX to allow ack and data reception
if (ack)
nrf24_writeRegister(NRF24_REG_RX_ADDR_P0, address, addr_width);
}
// --------------------------------------------------------------------------
void nrf24SetRxPipeAddress(UINT8 pipe_num, BYTE *address, BOOL enable)
{
if (pipe_num > NRF24_PIPE_COUNT_MAX)
return;
if (pipe_num < 2)
nrf24_writeRegister(NRF24_REG_RX_ADDR_P0 + pipe_num, (BYTE*)address, addr_width);
else
nrf24_writeRegister(NRF24_REG_RX_ADDR_P0 + pipe_num, (BYTE*)address, 1);
nrf24SetRxPipeEnabled(pipe_num, enable);
}
// --------------------------------------------------------------------------
static BOOL nrf24_writeByteRegister(UINT8 reg, BYTE *data)
{
BYTE read_val;
nrf24_writeRegister(reg, data, 1);
nrf24_readByteRegister(reg, &read_val);
return (read_val == *data);
}
/* Set the TX address */
void nrf24_tx_address(uint8_t* adr)
{
/* RX_ADDR_P0 must be set to the sending addr for auto ack to work. */
nrf24_writeRegister(RX_ADDR_P0,adr,nrf24_ADDR_LEN);
nrf24_writeRegister(TX_ADDR,adr,nrf24_ADDR_LEN);
}
/* Set the RX address */
void nrf24_rx_address(uint8_t * adr)
{
nrf24_ce_digitalWrite(LOW);
nrf24_writeRegister(RX_ADDR_P1,adr,nrf24_ADDR_LEN);
nrf24_ce_digitalWrite(HIGH);
}
// --------------------------------------------------------------------------
BOOL nrf24Init(const spi_cfg_st *spi_st)
{
u_nrf24_reg_t reg_val;
UINT8 i;
spi = (spi_cfg_st*)spi_st;
curr_mode = NRF24_MODE_POWERDOWN;
b_dynamic_payloads = false;
b_is_p_variant = false;
NRF24_CSN_HIGH();
NRF24_CE_LOW();
delayMs(100);
// initialize SPI and do some dummy reads to allow chip settle down
spiMasterInit(spi, SPI_CLK_POL_POS, SPI_CLK_PHA_SAMPLE, SPI_CLK_ORD_MSB);
for (i = 0; i < NRF24_STARTUP_REG_READ_CNT; ++i)
nrf24_readByteRegister(NRF24_REG_CONFIG, ®_val.byte);
reg_val.byte = 0;
nrf24_writeByteRegister(NRF24_REG_CONFIG, ®_val.byte);
// check communication
reg_val.CONFIG.EN_CRC = 1;
if (!nrf24_writeByteRegister(NRF24_REG_CONFIG, ®_val.byte))
{
nrf24_debug("communication problem, please check wiring\n");
return (false);
}
else
{
nrf24_debug("communication ok\n");
}
// check whether we have nrf24l01+ variant
reg_val.byte = 0;
reg_val.RF_SETUP_PLUS.RF_DR_LOW = 1;
if (nrf24_writeByteRegister(NRF24_REG_RF_SETUP, ®_val.byte))
{
nrf24_debug("detected nRF24L01+ chip\n");
b_is_p_variant = true;
}
else
{
nrf24_debug("detected nRF24L01 chip\n");
}
//
// SETUP PHASE
//
// disable chip by default
if (!nrf24SetMode(NRF24_MODE_POWERDOWN))
return (false);
// set 2 byte CRC by default
if (!nrf24SetCrcLength(NRF24_CRC_16))
return (false);
// set data rate to 1Mbps (most reliable and supported by all chips)
if (!nrf24SetDataRate(NRF24_DRATE_1M))
return (false);
// leave tx power at low level
if (!nrf24SetPowerLevel(NRF24_PL_LOW))
return (false);
// set default address width to 5 bytes
if (!nrf24SetAddressWidth(NRF24_ADRWIDTH_5))
return (false);
// set default channel in the middle of spectrum
if (!nrf24SetChannel(64))
return (false);
// set maximum delay (1500us) for retransmission (15 retries) to make testing easier
if (!nrf24SetAutoRetransmit(1500, 15))
return (false);
// disable auto acknowledgement on all pipes
reg_val.byte = 0;
nrf24_writeByteRegister(NRF24_REG_EN_AA, ®_val.byte);
// default receive pipe addresses
nrf24_writeRegister(NRF24_REG_RX_ADDR_P0, (BYTE*)"00000", 5);
nrf24_writeRegister(NRF24_REG_RX_ADDR_P1, (BYTE*)"11111", 5);
nrf24_writeRegister(NRF24_REG_RX_ADDR_P2, (BYTE*)"2", 1);
nrf24_writeRegister(NRF24_REG_RX_ADDR_P3, (BYTE*)"3", 1);
nrf24_writeRegister(NRF24_REG_RX_ADDR_P4, (BYTE*)"4", 1);
nrf24_writeRegister(NRF24_REG_RX_ADDR_P5, (BYTE*)"5", 1);
// default transmitter address
nrf24_writeRegister(NRF24_REG_TX_ADDR, (BYTE*)"00000", 5);
// disable all pipes
nrf24_writeByteRegister(NRF24_REG_EN_RXADDR, ®_val.byte);
// disable all receive pipes (no payload expected)
nrf24_writeByteRegister(NRF24_REG_RX_PW_P0, ®_val.byte);
nrf24_writeByteRegister(NRF24_REG_RX_PW_P1, ®_val.byte);
nrf24_writeByteRegister(NRF24_REG_RX_PW_P2, ®_val.byte);
nrf24_writeByteRegister(NRF24_REG_RX_PW_P3, ®_val.byte);
nrf24_writeByteRegister(NRF24_REG_RX_PW_P4, ®_val.byte);
nrf24_writeByteRegister(NRF24_REG_RX_PW_P5, ®_val.byte);
// activate disabled registers
nrf24_enableFeatures();
// disable dynamic payloads
reg_val.byte = 0;
if (!nrf24_writeByteRegister(NRF24_REG_DYNPD, ®_val.byte))
return (false);
if (!nrf24_writeByteRegister(NRF24_REG_FEATURE, ®_val.byte))
return (false);
// reset status
nrf24_resetStatus(true, true, true);
// flush tx and rx fifos
nrf24FlushRx();
nrf24FlushTx();
nrf24_debug("init ok\n");
return (true);
}
static void nrf24_test(void) {
uint8_t rx_address[5] = {0xA7,0x95,0xF1,0x36,0x07};
uint8_t tx_address[5] = {0xA7,0x95,0xF1,0x36,0x06};
//uint8_t tx_address[5] = {0x17,0x97,0xA7,0xA7,0xD7};
uint8_t addr[10] = {0x1};
uint8_t val = 0x17;
uint8_t reg;
uint8_t data_array[6];
uint32_t counter = 0;
spi_delay(1000000);
/* init hardware pins */
nrf24_init();
if (spi_init() < 0) {
printf("ERRRRROR SPI!\n");
}
/* Returned value is not correct on the first read, who knows why... */
nrf24_readRegister(CONFIG, ®, 1);
nrf24_readRegister(CONFIG, ®, 1);
printf("CONFIG (before configured) = %x\n", reg);
nrf24_readRegister(EN_AA, ®, 1);
printf("EN_AA = %x\n", reg);
nrf24_readRegister(RF_SETUP, ®, 1);
printf("RF_SETUP = %x\n", reg);
nrf24_readRegister(SETUP_AW, ®, 1);
printf("SETUP_AW = %x\n", reg);
nrf24_readRegister(SETUP_RETR, ®, 1);
printf("SETUP_RETR = %x\n", reg);
nrf24_readRegister(FIFO_STATUS, ®, 1);
printf("FIFO_STATUS = %x\n", reg);
nrf24_readRegister(RF_CH, ®, 1);
printf("RF_CH = %x\n", reg);
nrf24_writeRegister(RF_CH, &val, 1);
nrf24_readRegister(RF_CH, ®, 1);
printf("RF_CH = %x\n", reg);
val = 2;
nrf24_writeRegister(RF_CH, &val, 1);
nrf24_readRegister(RF_CH, ®, 1);
printf("RF_CH = %x\n", reg);
#if 1
nrf24_readRegister(RX_ADDR_P0, addr, 5);
printf("RX_ADDR_P0: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
nrf24_writeRegister(RX_ADDR_P0, tx_address,5);
spi_delay(1000000);
nrf24_readRegister(RX_ADDR_P0, addr, 5);
printf("RX_ADDR_P0: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
spi_delay(1000000);
nrf24_readRegister(RF_CH, ®, 1);
nrf24_readRegister(TX_ADDR, addr, 5);
printf("TX_ADDR: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
nrf24_writeRegister(TX_ADDR, tx_address,5);
nrf24_readRegister(TX_ADDR, addr, 5);
printf("TX_ADDR: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
spi_delay(1000000);
nrf24_readRegister(RX_ADDR_P1, addr, 5);
printf("RX_ADDR_P1: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
nrf24_writeRegister(RX_ADDR_P1, rx_address,5);
nrf24_readRegister(RX_ADDR_P1, addr, 5);
printf("RX_ADDR_P1: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
#endif
/* Channel #2 , payload length: 4 */
nrf24_config(16,6);
nrf24_readRegister(FIFO_STATUS,®,1);
printf("!> 1 FIFO_STATUS = %2X\n", reg);
spi_delay(1000000);
nrf24_readRegister(CONFIG, ®, 1);
nrf24_readRegister(CONFIG, ®, 1);
printf("CONFIG (after configured) = %x\n", reg);
nrf24_readRegister(EN_AA, ®, 1);
printf("EN_AA = %x\n", reg);
nrf24_readRegister(RF_SETUP, ®, 1);
printf("RF_SETUP = %x\n", reg);
nrf24_readRegister(TX_ADDR, addr, 5);
printf("TX addr is: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
//spi_delay(1000000);
nrf24_readRegister(RX_ADDR_P0, addr, 5);
printf("RX addr is: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
//spi_delay(1000000);
nrf24_readRegister(RX_ADDR_P1, addr, 5);
printf("RX_ADDR_P1 addr is: %x %x %x %x %x\n", addr[0], addr[1], addr[2], addr[3], addr[4]);
nrf24_readRegister(FIFO_STATUS,®,1);
printf("!!!!!!> 2 FIFO_STATUS = %2X\n", reg);
/* Set the device addresses */
//nrf24_tx_address(rx_address);
//nrf24_rx_address(rx_address);
//nrf24_ce_digitalWrite(HIGH);
//reg = nrf24_getStatus();
//printf("STATUS = %2X\n", reg);
nrf24_readRegister(FIFO_STATUS,®,1);
printf("!!!!!!> 3 FIFO_STATUS = %2X\n", reg);
while(1) {
if(nrf24_dataReady())
{
counter = 0;
//reg = nrf24_getStatus();
//printf("STATUS = %x\n", reg);
nrf24_getData(data_array);
printf("> ");
printf("%2X ",data_array[0]);
printf("%2X ",data_array[1]);
printf("%2X ",data_array[2]);
printf("%2X ",data_array[3]);
printf("%2X ",data_array[4]);
printf("%2X\r\n",data_array[5]);
//spi_delay(1000);
} else if (counter > 100000) {
reg = nrf24_getStatus();
printf("(counter > 100000) STATUS = %2X\n", reg);
nrf24_readRegister(FIFO_STATUS,®,1);
printf("(counter > 100000) FIFO_STATUS = %2X\n", reg);
}
counter++;
}
}
