static void radio_setup() { // Update RF231 config if board is patched if (al04_has_slptr_on_timer) { _rf231_config.slp_tr_gpio = GPIO_C; _rf231_config.slp_tr_pin = GPIO_PIN_6; _rf231_config.slp_tr_af = GPIO_AF_2; } // Configure the radio chips // Set IRQ as input IRQ syscfg_select_exti_pin(EXTI_LINE_Px0, SYSCFG_PORT_B); nvic_enable_interrupt_line(NVIC_IRQ_LINE_EXTI0); // Set DIG2 as Timer input capture gpio_set_alternate_function(GPIO_A, GPIO_PIN_6, GPIO_AF_3); // Initialize the radio to put it in Sleep State rf2xx_init(rf231); // Set IRQ as input IRQ syscfg_select_exti_pin(EXTI_LINE_Px1, SYSCFG_PORT_B); nvic_enable_interrupt_line(NVIC_IRQ_LINE_EXTI1); // Set DIG2 as Timer input capture gpio_set_alternate_function(GPIO_A, GPIO_PIN_7, GPIO_AF_3); // Initialize the radio to put it in Sleep State rf2xx_init(rf212); }
void ethmac_start(const uint8_t* address) { // Copy MAC address int i; for (i = 0; i < 6; i++) { mac.mac_address[i] = address[i]; } /* MAC clocks activation and commanded reset procedure.*/ *ethmac_get_DMABMR() |= ETHMAC_DMABMR__SR; while (*ethmac_get_DMABMR() & ETHMAC_DMABMR__SR) ; // Reset the descriptors ethmac_descriptors_reset(); /* ISR vector enabled.*/ nvic_enable_interrupt_line(NVIC_IRQ_LINE_ETH); /* PHY in power up mode.*/ mii_write(MII_BMCR, mii_read(MII_BMCR) & ~MII_BMCR__PDOWN); /* MAC configuration.*/ *ethmac_get_MACFFR() = 0; *ethmac_get_MACFCR() = 0; *ethmac_get_MACVLANTR() = 0; /* MAC address setup.*/ set_mac_address(mac.mac_address); /* Transmitter and receiver enabled. Note that the complete setup of the MAC is performed when the link status is detected.*/ // No checksum offload *ethmac_get_MACCR() = ETHMAC_MACCR__RE | ETHMAC_MACCR__TE; /* DMA configuration: Descriptor chains pointers.*/ *ethmac_get_DMARDLAR() = (uint32_t) ethmac_rx_des; *ethmac_get_DMATDLAR() = (uint32_t) ethmac_tx_des; /* Enabling required interrupt sources.*/ *ethmac_get_DMASR() = (uint32_t) (*ethmac_get_DMASR()); *ethmac_get_DMAIER() = ETHMAC_DMAIER__NISE | ETHMAC_DMAIER__AISE | ETHMAC_DMAIER__RIE | ETHMAC_DMAIER__TIE; /* DMA general settings.*/ *ethmac_get_DMABMR() = ETHMAC_DMABMR__AAB | ETHMAC_DMABMR__RDP_1Beat | ETHMAC_DMABMR__PBL_1Beat; /* Transmit FIFO flush.*/ *ethmac_get_DMAOMR() = ETHMAC_DMAOMR__FTF; while (*ethmac_get_DMAOMR() & ETHMAC_DMAOMR__FTF) ; /* DMA final configuration and start.*/ *ethmac_get_DMAOMR() = ETHMAC_DMAOMR__DTCEFD | ETHMAC_DMAOMR__RSF | ETHMAC_DMAOMR__TSF | ETHMAC_DMAOMR__ST | ETHMAC_DMAOMR__SR; }
static void power_setup() { /* * Configure the multiplexer: * EN: PC6 * A0: PC9 * A1: PC10 */ adg759_config(&ina_mux, GPIO_TYPE_PUSH_PULL); adg759_enable(&ina_mux); adg759_select(&ina_mux, ADG759_INPUT_1); log_printf("Configuring INA226...\n"); // Select PC0 as input interrupt (ALERT) gpio_set_input(GPIO_C, GPIO_PIN_0); afio_select_exti_pin(EXTI_LINE_Px0, AFIO_PORT_C); nvic_enable_interrupt_line(NVIC_IRQ_LINE_EXTI0); // Configure the INA226, then initialize ina226_init(I2C_1, 0x80, EXTI_LINE_Px0); // Initial calibration ina226_calibrate(1, 0.1); // Configure the fiteco lib fiteco_lib_gwt_set_config(&gwt_config); }
static void radio_setup() { // RF 231 // Set IRQ (PC4) as input IRQ gpio_set_input(GPIO_C, GPIO_PIN_4); afio_select_exti_pin(EXTI_LINE_Px4, AFIO_PORT_C); nvic_enable_interrupt_line(NVIC_IRQ_LINE_EXTI4); // Set DIG2 (PB0) as Timer 3 channel 3 input capture // Configure the Timer Capture pins gpio_set_input(GPIO_B, GPIO_PIN_0); // Initialize the radio to put it in Sleep State rf2xx_init(rf231); }
void platform_usb_enable() { // gpio_enable(GPIO_A); // gpio_set_alternate_function(GPIO_A, GPIO_PIN_11, GPIO_AF_10); // gpio_set_alternate_function(GPIO_A, GPIO_PIN_12, GPIO_AF_10); // external pull-up gpio_enable(GPIO_B); gpio_set_output(GPIO_B, GPIO_PIN_5); gpio_pin_set(GPIO_B, GPIO_PIN_5); // internal pull-up //syscfg_pmc_config(SYSCFG_PMC_USB, 1); nvic_enable_interrupt_line(NVIC_IRQ_LINE_USB_LP); }
void timer_enable(openlab_timer_t timer) { const _openlab_timer_t *_timer = timer; // Enable the clock for TIMx in the RCC registers rcc_apb_enable(_timer->apb_bus, _timer->apb_bit); // Clear the registers *timer_get_CR1(_timer) = 0; *timer_get_CR2(_timer) = 0; *timer_get_SMCR(_timer) = 0; *timer_get_DIER(_timer) = 0; *timer_get_SR(_timer) = 0; *timer_get_EGR(_timer) = 0; *timer_get_CCMRx(_timer, 1) = 0; *timer_get_CCMRx(_timer, 2) = 0; *timer_get_CCER(_timer) = 0; // Enable the interrupt in the NVIC nvic_enable_interrupt_line(_timer->irq_line); }
void i2c_enable(i2c_t i2c, i2c_clock_mode_t mode) { uint32_t pclk, freq; const _i2c_t *_i2c = i2c; // Disable the I2C EV and ERR interrupt lines in the NVIC nvic_disable_interrupt_line(_i2c->irq_line_ev); nvic_disable_interrupt_line(_i2c->irq_line_er); // Enable the clock for this peripheral rcc_apb_enable(_i2c->apb_bus, _i2c->apb_bit); // Reset the peripheral *i2c_get_CR1(_i2c) = I2C_CR1__SWRST; // Clear all registers *i2c_get_CR2(_i2c) = 0; *i2c_get_CCR(_i2c) = 0; *i2c_get_TRISE(_i2c) = 0; *i2c_get_SR1(_i2c) = 0; *i2c_get_SR2(_i2c) = 0; *i2c_get_OAR1(_i2c) = 0; *i2c_get_OAR2(_i2c) = 0; // Release SWRST *i2c_get_CR1(_i2c) = 0; /* Step 1: program the peripheral input clock in CR2 */ // Compute clock frequency pclk = rcc_sysclk_get_clock_frequency( _i2c->apb_bus == 1 ? RCC_SYSCLK_CLOCK_PCLK1 : RCC_SYSCLK_CLOCK_PCLK2); freq = pclk / 1000000; *i2c_get_CR2(_i2c) = freq & I2C_CR2__FREQ_MASK; /* Step 2: configure the clock control registers */ if (mode == I2C_CLOCK_MODE_FAST) { // Set Fast Speed mode and bitrate: ~400kHz uint32_t ccr = freq * 10; ccr = ccr / 12 + (ccr % 12 ? 1 : 0); *i2c_get_CCR(_i2c) = I2C_CCR__FS | ccr; } else { // Set Standard Speed mode and bitrate: 100kHz *i2c_get_CCR(_i2c) = (freq * 5) & I2C_CCR__CCR_MASK; } /* Step 3: configure the rise time registers */ if (mode == I2C_CLOCK_MODE_FAST) { // Configure maximum rise time *i2c_get_TRISE(_i2c) = (freq * 3 / 10 + 1) & I2C_TRISE__TRISE_MASK; } else { // Configure maximum rise time *i2c_get_TRISE(_i2c) = (freq + 1) & I2C_TRISE__TRISE_MASK; } /* Step 4: program the CR1 register to enable the peripheral */ // Enable I2C *i2c_get_CR1(_i2c) = I2C_CR1__PE; // Enable EVT and ERR interrupt // Note: do not enable BUF to avoid stm32f problem *i2c_get_CR2(_i2c) |= I2C_CR2__ITEVTEN | I2C_CR2__ITERREN; // Initialize I2C state _i2c->data->state = I2C_IDLE; _i2c->data->len_send = 0; _i2c->data->len_recv = 0; _i2c->data->cpt_send = 0; _i2c->data->cpt_recv = 0; _i2c->data->transfer_handler = NULL; // Enable I2C EV and ERR interrupt line in the NVIC nvic_enable_interrupt_line(_i2c->irq_line_ev); nvic_enable_interrupt_line(_i2c->irq_line_er); }
void i2c_enable(i2c_t i2c, i2c_clock_mode_t mode) { uint32_t pclk, freq; _i2c_t *_i2c = i2c; // Disable the I2C EV and ERR interrupt lines in the NVIC nvic_disable_interrupt_line(_i2c->irq_line_ev); nvic_disable_interrupt_line(_i2c->irq_line_er); // Enable the clock for this peripheral rcc_apb_enable(_i2c->apb_bus, _i2c->apb_bit); // Reset the peripheral *i2c_get_CR1(_i2c) = I2C_CR1__SWRST; // Clear all registers *i2c_get_CR1(_i2c) = 0; *i2c_get_CR2(_i2c) = 0; *i2c_get_CCR(_i2c) = 0; *i2c_get_TRISE(_i2c) = 0; *i2c_get_SR1(_i2c) = 0; *i2c_get_SR2(_i2c) = 0; /* Step 1: program the peripheral input clock in CR2 */ // Compute clock frequency pclk = rcc_sysclk_get_clock_frequency( _i2c->apb_bus == 1 ? RCC_SYSCLK_CLOCK_PCLK1 : RCC_SYSCLK_CLOCK_PCLK2); freq = pclk / 1000000; *i2c_get_CR2(_i2c) = freq & I2C_CR2__FREQ_MASK; /* Step 2: configure the clock control registers */ if (mode == I2C_CLOCK_MODE_FAST) { // Set Fast Speed mode and bitrate: 400kHz with duty t_low/t_high = 16/9 *i2c_get_CCR(_i2c) = I2C_CCR__FS | I2C_CCR__DUTY | (freq / 10 * 25); } else { // Set Standard Speed mode and bitrate: 100kHz *i2c_get_CCR(_i2c) = (freq * 5) & I2C_CCR__CCR_MASK; } /* Step 3: configure the rise time registers */ if (mode == I2C_CLOCK_MODE_FAST) { // Configure maximum rise time *i2c_get_TRISE(_i2c) = (freq * 3 / 10 + 1) & I2C_TRISE__TRISE_MASK; } else { // Configure maximum rise time *i2c_get_TRISE(_i2c) = (freq + 1) & I2C_TRISE__TRISE_MASK; } /* Step 4: program the CR1 register to enable the peripheral */ // Set I2C mode, enable ACK and enable I2C *i2c_get_CR1(_i2c) = I2C_CR1__ACK | I2C_CR1__PE; // Enable EV and BUF interrupt *i2c_get_CR2(_i2c) |= I2C_CR2__ITEVTEN | I2C_CR2__ITBUFEN | I2C_CR2__ITERREN; // Initialize I2C state state = I2C_IDLE; // Enable I2C EV and ERR interrupt line in the NVIC nvic_enable_interrupt_line(_i2c->irq_line_ev); nvic_enable_interrupt_line(_i2c->irq_line_er); }