int
octeon_eth_configure_common(struct octeon_eth_softc *sc)
{
static int once;
uint64_t reg;
if (once == 1)
return 0;
once = 1;
#if 0
octeon_eth_buf_init(sc);
#endif
cn30xxipd_config(sc->sc_ipd);
cn30xxpko_config(sc->sc_pko);
cn30xxpow_config(sc->sc_pow, OCTEON_POW_GROUP_PIP);
/* Set padding for packets that Octeon does not recognize as IP. */
reg = octeon_xkphys_read_8(PIP_GBL_CFG);
reg &= ~PIP_GBL_CFG_NIP_SHF_MASK;
reg |= ETHER_ALIGN << PIP_GBL_CFG_NIP_SHF_SHIFT;
octeon_xkphys_write_8(PIP_GBL_CFG, reg);
return 0;
}
int
octeon_eth_configure_common(struct octeon_eth_softc *sc)
{
static int once;
if (once == 1)
return 0;
once = 1;
#if 0
octeon_eth_buf_init(sc);
#endif
cn30xxipd_config(sc->sc_ipd);
cn30xxpko_config(sc->sc_pko);
cn30xxpow_config(sc->sc_pow, OCTEON_POW_GROUP_PIP);
return 0;
}
void
octeon_eth_attach(struct device *parent, struct device *self, void *aux)
{
struct octeon_eth_softc *sc = (void *)self;
struct cn30xxgmx_attach_args *ga = aux;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
uint8_t enaddr[ETHER_ADDR_LEN];
sc->sc_regt = ga->ga_regt;
sc->sc_dmat = ga->ga_dmat;
sc->sc_port = ga->ga_portno;
sc->sc_port_type = ga->ga_port_type;
sc->sc_gmx = ga->ga_gmx;
sc->sc_gmx_port = ga->ga_gmx_port;
sc->sc_phy_addr = ga->ga_phy_addr;
sc->sc_init_flag = 0;
/*
* XXX
* Setting PIP_IP_OFFSET[OFFSET] to 8 causes panic ... why???
*/
sc->sc_ip_offset = 0/* XXX */;
octeon_eth_board_mac_addr(enaddr);
printf(", address %s\n", ether_sprintf(enaddr));
octeon_eth_gsc[sc->sc_port] = sc;
ml_init(&sc->sc_sendq);
sc->sc_soft_req_thresh = 15/* XXX */;
sc->sc_ext_callback_cnt = 0;
cn30xxgmx_stats_init(sc->sc_gmx_port);
timeout_set(&sc->sc_tick_misc_ch, octeon_eth_tick_misc, sc);
timeout_set(&sc->sc_tick_free_ch, octeon_eth_tick_free, sc);
cn30xxfau_op_init(&sc->sc_fau_done,
OCTEON_CVMSEG_ETHER_OFFSET(sc->sc_port, csm_ether_fau_done),
OCT_FAU_REG_ADDR_END - (8 * (sc->sc_port + 1))/* XXX */);
cn30xxfau_op_set_8(&sc->sc_fau_done, 0);
octeon_eth_pip_init(sc);
octeon_eth_ipd_init(sc);
octeon_eth_pko_init(sc);
octeon_eth_asx_init(sc);
octeon_eth_smi_init(sc);
sc->sc_gmx_port->sc_ipd = sc->sc_ipd;
sc->sc_gmx_port->sc_port_asx = sc->sc_asx;
sc->sc_gmx_port->sc_port_mii = &sc->sc_mii;
sc->sc_gmx_port->sc_port_ac = &sc->sc_arpcom;
/* XXX */
sc->sc_pow = &cn30xxpow_softc;
octeon_eth_mediainit(sc);
strncpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof(ifp->if_xname));
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = octeon_eth_ioctl;
ifp->if_start = octeon_eth_start;
ifp->if_watchdog = octeon_eth_watchdog;
IFQ_SET_MAXLEN(&ifp->if_snd, max(GATHER_QUEUE_SIZE, IFQ_MAXLEN));
ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_TCPv4 |
IFCAP_CSUM_UDPv4 | IFCAP_CSUM_TCPv6 | IFCAP_CSUM_UDPv6;
cn30xxgmx_set_mac_addr(sc->sc_gmx_port, enaddr);
cn30xxgmx_set_filter(sc->sc_gmx_port);
if_attach(ifp);
memcpy(sc->sc_arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
ether_ifattach(ifp);
/* XXX */
sc->sc_rate_recv_check_link_cap.tv_sec = 1;
sc->sc_rate_recv_check_jumbo_cap.tv_sec = 1;
sc->sc_rate_recv_check_code_cap.tv_sec = 1;
#if 1
octeon_eth_buf_init(sc);
#endif
if (octeon_eth_pow_recv_ih == NULL)
octeon_eth_pow_recv_ih = cn30xxpow_intr_establish(
OCTEON_POW_GROUP_PIP, IPL_NET | IPL_MPSAFE,
octeon_eth_recv_intr, NULL, NULL, sc->sc_dev.dv_xname);
}
