static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->phyaddr = -1;
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
debug("phy-handle does exist %s\n", dev->name);
priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
priv->phy_of_node = phandle_args.node;
priv->max_speed = ofnode_read_u32_default(phandle_args.node,
"max-speed",
SPEED_1000);
}
phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static int gpio_dwapb_bind(struct udevice *dev)
{
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
struct udevice *subdev;
fdt_addr_t base;
int ret, bank = 0;
ofnode node;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE) {
debug("Can't get the GPIO register base address\n");
return -ENXIO;
}
for (node = dev_read_first_subnode(dev); ofnode_valid(node);
node = dev_read_next_subnode(node)) {
if (!ofnode_read_bool(node, "gpio-controller"))
continue;
plat = devm_kcalloc(dev, 1, sizeof(*plat), GFP_KERNEL);
if (!plat)
return -ENOMEM;
plat->base = base;
plat->bank = bank;
plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
if (ofnode_read_string_index(node, "bank-name", 0,
&plat->name)) {
/*
* Fall back to node name. This means accessing pins
* via bank name won't work.
*/
plat->name = ofnode_get_name(node);
}
ret = device_bind(dev, dev->driver, plat->name,
plat, -1, &subdev);
if (ret)
return ret;
dev->node = node;
bank++;
}
return 0;
}
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
struct bank_params *bank_params;
struct ofnode_phandle_args args;
u32 *syscfg_base;
u32 mem_remap;
u32 swp_fmc;
ofnode bank_node;
char *bank_name;
u8 bank = 0;
int ret;
ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (ret) {
dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
} else {
syscfg_base = (u32 *)ofnode_get_addr(args.node);
mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
if (mem_remap != NOT_FOUND) {
/* set memory mapping selection */
clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
} else {
dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
}
swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
if (swp_fmc != NOT_FOUND) {
/* set fmc swapping selection */
clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
} else {
dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
}
dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
}
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
bank_name = (char *)ofnode_get_name(bank_node);
strsep(&bank_name, "@");
if (!bank_name) {
pr_err("missing sdram bank index");
return -EINVAL;
}
bank_params = ¶ms->bank_params[bank];
strict_strtoul(bank_name, 10,
(long unsigned int *)&bank_params->target_bank);
if (bank_params->target_bank >= MAX_SDRAM_BANK) {
pr_err("Found bank %d , but only bank 0 and 1 are supported",
bank_params->target_bank);
return -EINVAL;
}
debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
params->bank_params[bank].sdram_control =
(struct stm32_sdram_control *)
ofnode_read_u8_array_ptr(bank_node,
"st,sdram-control",
sizeof(struct stm32_sdram_control));
if (!params->bank_params[bank].sdram_control) {
pr_err("st,sdram-control not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
params->bank_params[bank].sdram_timing =
(struct stm32_sdram_timing *)
ofnode_read_u8_array_ptr(bank_node,
"st,sdram-timing",
sizeof(struct stm32_sdram_timing));
if (!params->bank_params[bank].sdram_timing) {
pr_err("st,sdram-timing not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
"st,sdram-refcount", 8196);
bank++;
}
int dev_read_u32_default(struct udevice *dev, const char *propname, int def)
{
return ofnode_read_u32_default(dev_ofnode(dev), propname, def);
}
