void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) { if (omap_hsmmc_done) return; omap_hsmmc_done = 1; if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } for (; controllers->mmc; controllers++) omap_hsmmc_init_one(controllers, controllers->mmc); }
void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) { u32 reg; if (omap_hsmmc_done) return; omap_hsmmc_done = 1; if (!(cpu_is_omap44xx() || cpu_is_omap54xx())) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else if (cpu_is_omap44xx()) { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } else if (cpu_is_omap54xx()) { control_pbias_offset = OMAP5_CTRL_MODULE_CORE_PAD_CONTROL_PBIAS; } for (; controllers->mmc; controllers++) omap_hsmmc_init_one(controllers, controllers->mmc); }