int
omgpio_irq(void *v)
{
struct omgpio_softc *sc = v;
u_int32_t pending;
struct intrhand *ih;
int bit;
pending = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_IRQSTATUS1);
while (pending != 0) {
bit = ffs(pending) - 1;
ih = sc->sc_handlers[bit];
if (ih != NULL) {
if (ih->ih_func(ih->ih_arg))
ih->ih_count.ec_count++;
omgpio_clear_intr(ih->ih_gpio);
} else {
panic("omgpio: irq fired no handler, gpio %x %x %x",
sc->sc_dev.dv_unit * 32 + bit, pending,
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_IRQENABLE1)
);
}
pending &= ~(1 << bit);
}
return 1;
}
int
omgpio_irq(void *v)
{
struct omgpio_softc *sc = v;
u_int32_t pending;
struct intrhand *ih;
int bit;
pending = READ4(sc, omgpio.irqstatus0);
while (pending != 0) {
bit = ffs(pending) - 1;
ih = sc->sc_handlers[bit];
if (ih != NULL) {
if (ih->ih_func(ih->ih_arg))
ih->ih_count.ec_count++;
omgpio_clear_intr(ih->ih_gpio);
} else {
panic("omgpio: irq fired no handler, gpio %x %x %x",
sc->sc_dev.dv_unit * 32 + bit, pending,
READ4(sc, omgpio.irqstatus0)
);
}
pending &= ~(1 << bit);
}
return 1;
}
void
omgpio_intr_disestablish(void *cookie)
{
int psw;
struct intrhand *ih = cookie;
struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(ih->ih_gpio)];
int gpio = ih->ih_gpio;
psw = disable_interrupts(I32_bit);
ih = sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)];
sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)] = NULL;
evcount_detach(&ih->ih_count);
free(ih, M_DEVBUF);
omgpio_intr_level(gpio, IST_NONE);
omgpio_intr_mask(gpio);
omgpio_clear_intr(gpio); /* Just in case */
omgpio_recalc_interrupts(sc);
restore_interrupts(psw);
}
