/*
* 64-bit 3way compare function.
* mov r7, #-1
* cmp op1hi, op2hi
* blt done
* bgt flip
* sub r7, op1lo, op2lo (treat as unsigned)
* beq done
* ite hi
* mov(hi) r7, #-1
* mov(!hi) r7, #1
* flip:
* neg r7
* done:
*/
static void genCmpLong(CompilationUnit *cUnit, MIR *mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
RegLocation rlTemp = LOC_C_RETURN; // Just using as template, will change
ArmLIR *target1;
ArmLIR *target2;
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
rlTemp.lowReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, rlTemp.lowReg, -1);
opRegReg(cUnit, kOpCmp, rlSrc1.highReg, rlSrc2.highReg);
ArmLIR *branch1 = opCondBranch(cUnit, kArmCondLt);
ArmLIR *branch2 = opCondBranch(cUnit, kArmCondGt);
opRegRegReg(cUnit, kOpSub, rlTemp.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
ArmLIR *branch3 = opCondBranch(cUnit, kArmCondEq);
genIT(cUnit, kArmCondHi, "E");
newLIR2(cUnit, kThumb2MovImmShift, rlTemp.lowReg, modifiedImmediate(-1));
loadConstant(cUnit, rlTemp.lowReg, 1);
genBarrier(cUnit);
target2 = newLIR0(cUnit, kArmPseudoTargetLabel);
target2->defMask = -1;
opRegReg(cUnit, kOpNeg, rlTemp.lowReg, rlTemp.lowReg);
target1 = newLIR0(cUnit, kArmPseudoTargetLabel);
target1->defMask = -1;
storeValue(cUnit, rlDest, rlTemp);
branch1->generic.target = (LIR *)target1;
branch2->generic.target = (LIR *)target2;
branch3->generic.target = branch1->generic.target;
}
/*
* Load a immediate using a shortcut if possible; otherwise
* grab from the per-translation literal pool. If target is
* a high register, build constant into a low register and copy.
*
* No additional register clobbering operation performed. Use this version when
* 1) rDest is freshly returned from dvmCompilerAllocTemp or
* 2) The codegen is under fixed register usage
*/
static ArmLIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest,
int value)
{
ArmLIR *res;
int tDest = LOWREG(rDest) ? rDest : dvmCompilerAllocTemp(cUnit);
/* See if the value can be constructed cheaply */
if ((value >= 0) && (value <= 255)) {
res = newLIR2(cUnit, kThumbMovImm, tDest, value);
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
} else if ((value & 0xFFFFFF00) == 0xFFFFFF00) {
res = newLIR2(cUnit, kThumbMovImm, tDest, ~value);
newLIR2(cUnit, kThumbMvn, tDest, tDest);
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
}
/* No shortcut - go ahead and use literal pool */
ArmLIR *dataTarget = scanLiteralPool(cUnit->literalList, value, 255);
if (dataTarget == NULL) {
dataTarget = addWordData(cUnit, &cUnit->literalList, value);
}
ArmLIR *loadPcRel = (ArmLIR *) dvmCompilerNew(sizeof(ArmLIR), true);
loadPcRel->opcode = kThumbLdrPcRel;
loadPcRel->generic.target = (LIR *) dataTarget;
loadPcRel->operands[0] = tDest;
setupResourceMasks(loadPcRel);
setMemRefType(loadPcRel, true, kLiteral);
loadPcRel->aliasInfo = dataTarget->operands[0];
res = loadPcRel;
dvmCompilerAppendLIR(cUnit, (LIR *) loadPcRel);
/*
* To save space in the constant pool, we use the ADD_RRI8 instruction to
* add up to 255 to an existing constant value.
*/
if (dataTarget->operands[0] != value) {
newLIR2(cUnit, kThumbAddRI8, tDest, value - dataTarget->operands[0]);
}
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
}
static bool genInlinedMinMaxInt(CompilationUnit *cUnit, MIR *mir, bool isMin)
{
RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);
RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg);
genIT(cUnit, (isMin) ? kArmCondGt : kArmCondLt, "E");
opRegReg(cUnit, kOpMov, rlResult.lowReg, rlSrc2.lowReg);
opRegReg(cUnit, kOpMov, rlResult.lowReg, rlSrc1.lowReg);
genBarrier(cUnit);
storeValue(cUnit, rlDest, rlResult);
return false;
}
/*
* Perform a "reg cmp reg" operation and jump to the PCR region if condition
* satisfies.
*/
static ArmLIR *genRegRegCheck(CompilationUnit *cUnit,
ArmConditionCode cond,
int reg1, int reg2, int dOffset,
ArmLIR *pcrLabel)
{
ArmLIR *res;
res = opRegReg(cUnit, kOpCmp, reg1, reg2);
ArmLIR *branch = opCondBranch(cUnit, cond);
genCheckCommon(cUnit, dOffset, branch, pcrLabel);
return res;
}
/*
* For monitor unlock, we don't have to use ldrex/strex. Once
* we've determined that the lock is thin and that we own it with
* a zero recursion count, it's safe to punch it back to the
* initial, unlock thin state with a store word.
*/
static void genMonitorExit(CompilationUnit *cUnit, MIR *mir)
{
RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
ArmLIR *target;
ArmLIR *branch;
ArmLIR *hopTarget;
ArmLIR *hopBranch;
assert(LW_SHAPE_THIN == 0);
loadValueDirectFixed(cUnit, rlSrc, r1); // Get obj
dvmCompilerLockAllTemps(cUnit); // Prepare for explicit register usage
dvmCompilerFreeTemp(cUnit, r4PC); // Free up r4 for general use
genNullCheck(cUnit, rlSrc.sRegLow, r1, mir->offset, NULL);
loadWordDisp(cUnit, r1, offsetof(Object, lock), r2); // Get object->lock
loadWordDisp(cUnit, r6SELF, offsetof(Thread, threadId), r3); // Get threadId
// Is lock unheld on lock or held by us (==threadId) on unlock?
opRegRegImm(cUnit, kOpAnd, r7, r2,
(LW_HASH_STATE_MASK << LW_HASH_STATE_SHIFT));
opRegImm(cUnit, kOpLsl, r3, LW_LOCK_OWNER_SHIFT); // Align owner
newLIR3(cUnit, kThumb2Bfc, r2, LW_HASH_STATE_SHIFT,
LW_LOCK_OWNER_SHIFT - 1);
opRegReg(cUnit, kOpSub, r2, r3);
hopBranch = opCondBranch(cUnit, kArmCondNe);
dvmCompilerGenMemBarrier(cUnit, kSY);
storeWordDisp(cUnit, r1, offsetof(Object, lock), r7);
branch = opNone(cUnit, kOpUncondBr);
hopTarget = newLIR0(cUnit, kArmPseudoTargetLabel);
hopTarget->defMask = ENCODE_ALL;
hopBranch->generic.target = (LIR *)hopTarget;
// Export PC (part 1)
loadConstant(cUnit, r3, (int) (cUnit->method->insns + mir->offset));
LOAD_FUNC_ADDR(cUnit, r7, (int)dvmUnlockObject);
genRegCopy(cUnit, r0, r6SELF);
// Export PC (part 2)
newLIR3(cUnit, kThumb2StrRRI8Predec, r3, r5FP,
sizeof(StackSaveArea) -
offsetof(StackSaveArea, xtra.currentPc));
opReg(cUnit, kOpBlx, r7);
/* Did we throw? */
ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
loadConstant(cUnit, r0,
(int) (cUnit->method->insns + mir->offset +
dexGetWidthFromOpcode(OP_MONITOR_EXIT)));
genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
// Resume here
target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
branch->generic.target = (LIR *)target;
branchOver->generic.target = (LIR *) target;
}
static void genLong3Addr(CompilationUnit *cUnit, MIR *mir, OpKind firstOp,
OpKind secondOp, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
RegLocation rlResult;
if (partialOverlap(rlSrc1.sRegLow,rlSrc2.sRegLow) ||
partialOverlap(rlSrc1.sRegLow,rlDest.sRegLow) ||
partialOverlap(rlSrc2.sRegLow,rlDest.sRegLow)) {
// Rare case - not enough registers to properly handle
genInterpSingleStep(cUnit, mir);
} else if (rlDest.sRegLow == rlSrc1.sRegLow) {
// Already 2-operand
rlResult = loadValueWide(cUnit, rlDest, kCoreReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
opRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc2.lowReg);
opRegReg(cUnit, secondOp, rlResult.highReg, rlSrc2.highReg);
storeValueWide(cUnit, rlDest, rlResult);
} else if (rlDest.sRegLow == rlSrc2.sRegLow) {
// Bad case - must use/clobber Src1 and reassign Dest
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
rlResult = loadValueWide(cUnit, rlDest, kCoreReg);
opRegReg(cUnit, firstOp, rlSrc1.lowReg, rlResult.lowReg);
opRegReg(cUnit, secondOp, rlSrc1.highReg, rlResult.highReg);
// Old reg assignments are now invalid
dvmCompilerClobber(cUnit, rlResult.lowReg);
dvmCompilerClobber(cUnit, rlResult.highReg);
dvmCompilerClobber(cUnit, rlSrc1.lowReg);
dvmCompilerClobber(cUnit, rlSrc1.highReg);
rlDest.location = kLocDalvikFrame;
assert(rlSrc1.location == kLocPhysReg);
// Reassign registers - rlDest will now get rlSrc1's old regs
storeValueWide(cUnit, rlDest, rlSrc1);
} else {
// Copy Src1 to Dest
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, false);
loadValueDirectWide(cUnit, rlSrc1, rlResult.lowReg,
rlResult.highReg);
rlResult.location = kLocPhysReg;
opRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc2.lowReg);
opRegReg(cUnit, secondOp, rlResult.highReg, rlSrc2.highReg);
storeValueWide(cUnit, rlDest, rlResult);
}
}
/*
* Generate array store
*
*/
static void genArrayPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
RegLocation rlArray, RegLocation rlIndex,
RegLocation rlSrc, int scale)
{
RegisterClass regClass = dvmCompilerRegClassBySize(size);
int lenOffset = OFFSETOF_MEMBER(ArrayObject, length);
int dataOffset = OFFSETOF_MEMBER(ArrayObject, contents);
int regPtr;
rlArray = loadValue(cUnit, rlArray, kCoreReg);
rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
if (dvmCompilerIsTemp(cUnit, rlArray.lowReg)) {
dvmCompilerClobber(cUnit, rlArray.lowReg);
regPtr = rlArray.lowReg;
} else {
regPtr = dvmCompilerAllocTemp(cUnit);
genRegCopy(cUnit, regPtr, rlArray.lowReg);
}
/* null object? */
ArmLIR * pcrLabel = NULL;
if (!(mir->OptimizationFlags & MIR_IGNORE_NULL_CHECK)) {
pcrLabel = genNullCheck(cUnit, rlArray.sRegLow, rlArray.lowReg,
mir->offset, NULL);
}
if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
int regLen = dvmCompilerAllocTemp(cUnit);
//NOTE: max live temps(4) here.
/* Get len */
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
/* regPtr -> array data */
opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
pcrLabel);
dvmCompilerFreeTemp(cUnit, regLen);
} else {
/* regPtr -> array data */
opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
}
/* at this point, regPtr points to array, 2 live temps */
if ((size == kLong) || (size == kDouble)) {
//TODO: need specific wide routine that can handle fp regs
if (scale) {
int rNewIndex = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
} else {
opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
}
rlSrc = loadValueWide(cUnit, rlSrc, regClass);
HEAP_ACCESS_SHADOW(true);
storePair(cUnit, regPtr, rlSrc.lowReg, rlSrc.highReg);
HEAP_ACCESS_SHADOW(false);
dvmCompilerFreeTemp(cUnit, regPtr);
} else {
rlSrc = loadValue(cUnit, rlSrc, regClass);
HEAP_ACCESS_SHADOW(true);
storeBaseIndexed(cUnit, regPtr, rlIndex.lowReg, rlSrc.lowReg,
scale, size);
HEAP_ACCESS_SHADOW(false);
}
}
/*
* Generate array load
*/
static void genArrayGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
RegLocation rlArray, RegLocation rlIndex,
RegLocation rlDest, int scale)
{
RegisterClass regClass = dvmCompilerRegClassBySize(size);
int lenOffset = OFFSETOF_MEMBER(ArrayObject, length);
int dataOffset = OFFSETOF_MEMBER(ArrayObject, contents);
RegLocation rlResult;
rlArray = loadValue(cUnit, rlArray, kCoreReg);
rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
int regPtr;
/* null object? */
ArmLIR * pcrLabel = NULL;
if (!(mir->OptimizationFlags & MIR_IGNORE_NULL_CHECK)) {
pcrLabel = genNullCheck(cUnit, rlArray.sRegLow,
rlArray.lowReg, mir->offset, NULL);
}
regPtr = dvmCompilerAllocTemp(cUnit);
if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
int regLen = dvmCompilerAllocTemp(cUnit);
/* Get len */
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
/* regPtr -> array data */
opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
pcrLabel);
dvmCompilerFreeTemp(cUnit, regLen);
} else {
/* regPtr -> array data */
opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
}
if ((size == kLong) || (size == kDouble)) {
if (scale) {
int rNewIndex = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
dvmCompilerFreeTemp(cUnit, rNewIndex);
} else {
opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
}
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
HEAP_ACCESS_SHADOW(true);
loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg);
HEAP_ACCESS_SHADOW(false);
dvmCompilerFreeTemp(cUnit, regPtr);
storeValueWide(cUnit, rlDest, rlResult);
} else {
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
HEAP_ACCESS_SHADOW(true);
loadBaseIndexed(cUnit, regPtr, rlIndex.lowReg, rlResult.lowReg,
scale, size);
HEAP_ACCESS_SHADOW(false);
dvmCompilerFreeTemp(cUnit, regPtr);
storeValue(cUnit, rlDest, rlResult);
}
}
