static void omap_set_vbus(struct musb *musb, int is_on)
{
u8 devctl;
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (is_on) {
musb->is_active = 1;
musb->xceiv->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
devctl |= MUSB_DEVCTL_SESSION;
MUSB_HST_MODE(musb);
} else {
musb->is_active = 0;
musb->xceiv->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
devctl &= ~MUSB_DEVCTL_SESSION;
MUSB_DEV_MODE(musb);
}
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x "
"\n",
otg_state_string(musb),
musb_readb(musb->mregs, MUSB_DEVCTL));
}
static void m2s_usb_vbus_set(struct musb *musb, int is_on)
{
u8 devctl;
/* HDRC controls CPEN, but beware current surges during device
* connect. They can trigger transient overcurrent conditions
* that must be ignored.
*/
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (is_on) {
musb->is_active = 1;
musb->xceiv->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
devctl |= MUSB_DEVCTL_SESSION;
MUSB_HST_MODE(musb);
} else {
musb->is_active = 0;
/* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
* jumping right to B_IDLE...
*/
musb->xceiv->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
devctl &= ~MUSB_DEVCTL_SESSION;
MUSB_DEV_MODE(musb);
}
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x\n",
otg_state_string(musb),
musb_readb(musb->mregs, MUSB_DEVCTL));
}
void musb_root_disconnect(struct musb *musb)
{
musb->port1_status = USB_PORT_STAT_POWER
| (USB_PORT_STAT_C_CONNECTION << 16);
usb_hcd_poll_rh_status(musb_to_hcd(musb));
musb->is_active = 0;
switch (musb->xceiv->state) {
case OTG_STATE_A_SUSPEND:
#ifdef CONFIG_USB_MUSB_OTG
if (is_otg_enabled(musb)
&& musb->xceiv->host->b_hnp_enable) {
musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
musb->g.is_a_peripheral = 1;
break;
}
#endif
/* FALLTHROUGH */
case OTG_STATE_A_HOST:
musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
musb->is_active = 0;
break;
case OTG_STATE_A_WAIT_VFALL:
musb->xceiv->state = OTG_STATE_B_IDLE;
break;
default:
DBG(1, "host disconnect (%s)\n", otg_state_string(musb));
}
}
void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
{
unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
static unsigned long last_timer;
u32 val;
if (timeout == 0)
timeout = default_timeout;
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || ((musb->a_wait_bcon == 0)
&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
del_timer(&musb_idle_timer);
last_timer = jiffies;
return;
}
if (musb->xceiv->state == OTG_STATE_UNDEFINED) {
/* disable the phy clock when the gadget driver is unloaded.
* Powerdown the phy and configure the musb sysconfig to
* force standby/idle.
* this will allow the core to hit retention and offmode
*/
otg_shutdown(musb->xceiv);
/* configure in force idle/ standby */
val = musb_readl(musb->mregs, OTG_SYSCONFIG);
val &= ~(SMARTIDLEWKUP | SMARTSTDBY | NOSTDBY | ENABLEWAKEUP);
val |= FORCEIDLE | FORCESTDBY;
musb_writel(musb->mregs, OTG_SYSCONFIG, val);
musb_writel(musb->mregs, OTG_FORCESTDBY, 1);
}
if (time_after(last_timer, timeout)) {
if (!timer_pending(&musb_idle_timer))
last_timer = timeout;
else {
DBG(4, "Longer idle timer already pending, ignoring\n");
return;
}
}
last_timer = timeout;
DBG(4, "%s inactive, for idle timer for %lu ms\n",
otg_state_string(musb),
(unsigned long)jiffies_to_msecs(timeout - jiffies));
mod_timer(&musb_idle_timer, timeout);
}
static void otg_timer(unsigned long _musb)
{
struct musb *musb = (void *)_musb;
void __iomem *mregs = musb->mregs;
u8 devctl;
unsigned long flags;
/* We poll because DaVinci's won't expose several OTG-critical
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
case OTG_STATE_A_WAIT_VFALL:
/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
* seems to mis-handle session "start" otherwise (or in our
* case "recover"), in routine "VBUS was valid by the time
* VBUSERR got reported during enumeration" cases.
*/
if (devctl & MUSB_DEVCTL_VBUS) {
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
break;
}
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
break;
case OTG_STATE_B_IDLE:
if (!is_peripheral_enabled(musb))
break;
/* There's no ID-changed IRQ, so we have no good way to tell
* when to switch to the A-Default state machine (by setting
* the DEVCTL.SESSION flag).
*
* Workaround: whenever we're in B_IDLE, try setting the
* session flag every few seconds. If it works, ID was
* grounded and we're now in the A-Default state machine.
*
* NOTE setting the session flag is _supposed_ to trigger
* SRP, but clearly it doesn't.
*/
/* musb_writeb(mregs, MUSB_DEVCTL,
devctl | MUSB_DEVCTL_SESSION);
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
if (devctl & MUSB_DEVCTL_BDEVICE)
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
else
musb->xceiv->state = OTG_STATE_A_IDLE;
break;
default:
break;
}
spin_unlock_irqrestore(&musb->lock, flags);
}
static void otg_timer(unsigned long _musb)
{
struct musb *musb = (void *)_musb;
void __iomem *mregs = musb->mregs;
struct device *dev = musb->controller;
struct platform_device *pdev = to_platform_device(dev);
struct dsps_glue *glue = dev_get_drvdata(dev->parent);
const struct dsps_musb_wrapper *wrp = glue->wrp;
u8 devctl;
unsigned long flags;
/*
* We poll because DSPS IP's won't expose several OTG-critical
* status change events (from the transceiver) otherwise.
*/
devctl = dsps_readb(mregs, MUSB_DEVCTL);
dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
case OTG_STATE_A_WAIT_BCON:
/*
* We need to avoid stopping the session in host mode,
* otherwise we don't see any newly connected devices
*/
if (!is_host_active(musb)) {
devctl &= ~MUSB_DEVCTL_SESSION;
dsps_writeb(musb->mregs, MUSB_DEVCTL, devctl);
}
devctl = dsps_readb(musb->mregs, MUSB_DEVCTL);
if (devctl & MUSB_DEVCTL_BDEVICE) {
musb->xceiv->state = OTG_STATE_B_IDLE;
MUSB_DEV_MODE(musb);
} else {
musb->xceiv->state = OTG_STATE_A_IDLE;
MUSB_HST_MODE(musb);
}
break;
case OTG_STATE_A_WAIT_VFALL:
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
dsps_writel(musb->ctrl_base, wrp->coreintr_set,
MUSB_INTR_VBUSERROR << wrp->usb_shift);
break;
case OTG_STATE_B_IDLE:
devctl = dsps_readb(mregs, MUSB_DEVCTL);
if (devctl & MUSB_DEVCTL_BDEVICE)
mod_timer(&glue->timer[pdev->id],
jiffies + wrp->poll_seconds * HZ);
else
musb->xceiv->state = OTG_STATE_A_IDLE;
break;
default:
break;
}
spin_unlock_irqrestore(&musb->lock, flags);
}
static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
{
u8 devctl;
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
int ret = 1;
/* HDRC controls CPEN, but beware current surges during device
* connect. They can trigger transient overcurrent conditions
* that must be ignored.
*/
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (is_on) {
if (musb->xceiv->state == OTG_STATE_A_IDLE) {
/* start the session */
devctl |= MUSB_DEVCTL_SESSION;
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
/*
* Wait for the musb to set as A device to enable the
* VBUS
*/
while (musb_readb(musb->mregs, MUSB_DEVCTL) & 0x80) {
cpu_relax();
if (time_after(jiffies, timeout)) {
dev_err(musb->controller,
"configured as A device timeout");
ret = -EINVAL;
break;
}
}
if (ret && musb->xceiv->set_vbus)
otg_set_vbus(musb->xceiv, 1);
musb->xceiv->default_a = 1;
MUSB_HST_MODE(musb);
}
} else {
musb->is_active = 0;
/* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
* jumping right to B_IDLE...
*/
musb->xceiv->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
devctl &= ~MUSB_DEVCTL_SESSION;
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
MUSB_DEV_MODE(musb);
}
dev_dbg(musb->controller, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
}
static ssize_t
exynos_drd_switch_show_state(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct exynos_drd *drd = dev_get_drvdata(dev);
struct usb_otg *otg = drd->core.otg;
struct usb_phy *phy = otg->phy;
return snprintf(buf, PAGE_SIZE, "%s\n", otg_state_string(phy->state));
}
static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
{
struct usb_otg *otg = musb->xceiv->otg;
u8 devctl;
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
int ret = 1;
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (is_on) {
if (musb->xceiv->state == OTG_STATE_A_IDLE) {
devctl |= MUSB_DEVCTL_SESSION;
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
while (musb_readb(musb->mregs, MUSB_DEVCTL) & 0x80) {
cpu_relax();
if (time_after(jiffies, timeout)) {
dev_err(musb->controller,
"configured as A device timeout");
ret = -EINVAL;
break;
}
}
if (ret && otg->set_vbus)
otg_set_vbus(otg, 1);
} else {
musb->is_active = 1;
otg->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
devctl |= MUSB_DEVCTL_SESSION;
MUSB_HST_MODE(musb);
}
} else {
musb->is_active = 0;
otg->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
devctl &= ~MUSB_DEVCTL_SESSION;
MUSB_DEV_MODE(musb);
}
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
dev_dbg(musb->controller, "VBUS %s, devctl %02x "
"\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
}
/**
* musb_platform_try_idle() - Check the USB state active or not.
* @musb: struct musb pointer.
* @timeout: set the timeout to keep the host in idle mode.
*
* This function keeps the USB host in idle state based on the musb inforamtion.
*/
void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
{
if (musb->board_mode != MUSB_PERIPHERAL) {
unsigned long default_timeout =
jiffies + msecs_to_jiffies(10);
static unsigned long last_timer;
if (timeout == 0)
timeout = default_timeout;
/* Never idle if active, or when VBUS
timeout is not set as host */
if (musb->is_active || ((musb->a_wait_bcon == 0)
&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
DBG(4, "%s active, deleting timer\n",
otg_state_string(musb));
del_timer(¬ify_timer);
last_timer = jiffies;
return;
}
if (time_after(last_timer, timeout)) {
if (!timer_pending(¬ify_timer))
last_timer = timeout;
else {
DBG(4,
"Longer idle timer already pending,ignoring\n");
return;
}
}
last_timer = timeout;
DBG(4, "%s inactive, for idle timer for %lu ms\n",
otg_state_string(musb),
(unsigned long)jiffies_to_msecs(timeout - jiffies));
mod_timer(¬ify_timer, timeout);
}
}
static void otg_timer(unsigned long _musb)
{
struct musb *musb = (void *)_musb;
void __iomem *mregs = musb->mregs;
u8 devctl;
unsigned long flags;
/*
* We poll because AM35x's won't expose several OTG-critical
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
case OTG_STATE_A_WAIT_BCON:
devctl &= ~MUSB_DEVCTL_SESSION;
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (devctl & MUSB_DEVCTL_BDEVICE) {
musb->xceiv->state = OTG_STATE_B_IDLE;
MUSB_DEV_MODE(musb);
} else {
musb->xceiv->state = OTG_STATE_A_IDLE;
MUSB_HST_MODE(musb);
}
break;
case OTG_STATE_A_WAIT_VFALL:
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
break;
case OTG_STATE_B_IDLE:
if (!is_peripheral_enabled(musb))
break;
devctl = musb_readb(mregs, MUSB_DEVCTL);
if (devctl & MUSB_DEVCTL_BDEVICE)
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
else
musb->xceiv->state = OTG_STATE_A_IDLE;
break;
default:
break;
}
spin_unlock_irqrestore(&musb->lock, flags);
}
/**
* set_vbus() - Set the Vbus for the USB.
* @musb: struct musb pointer.
* @is_on: set Vbus for USB or not.
*
* This function set the Vbus for USB.
*/
static void set_vbus(struct musb *musb, int is_on)
{
u8 devctl, val;
/* HDRC controls CPEN, but beware current surges during device
* connect. They can trigger transient overcurrent conditions
* that must be ignored.
*/
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (is_on) {
musb->is_active = 1;
musb->xceiv->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
devctl |= MUSB_DEVCTL_SESSION;
MUSB_HST_MODE(musb);
} else {
musb->is_active = 0;
/* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
* jumping right to B_IDLE...
*/
musb->xceiv->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
devctl &= ~MUSB_DEVCTL_SESSION;
MUSB_DEV_MODE(musb);
}
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb),
musb_readb(musb->mregs, MUSB_DEVCTL));
if (!is_on) {
/* Discahrge the VBUS */
if (musb_status == NULL)
return;
ulpi_write_register(musb_status, ULPI_OCTRL, 0x08);
val = ulpi_read_register(musb_status, ULPI_OCTRL);
DBG(1, "ULPI_OCTRL= %02x", val);
}
}
/**
* funct_host_notify_timer() - Initialize the timer for USB host driver.
* @data: usb host data.
*
* This function runs the timer for the USB host mode.
*/
static void funct_host_notify_timer(unsigned long data)
{
if (!cpu_is_u5500()) {
struct musb *musb = (struct musb *)data;
unsigned long flags;
u8 devctl;
spin_lock_irqsave(&musb->lock, flags);
stm_set_peripheral_clock(PERI5_CLK_ENABLE);
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
switch (musb->xceiv->state) {
case OTG_STATE_A_WAIT_BCON:
if (devctl & MUSB_DEVCTL_BDEVICE) {
musb->xceiv->state = OTG_STATE_B_IDLE;
MUSB_DEV_MODE(musb);
} else {
musb->xceiv->state = OTG_STATE_A_IDLE;
MUSB_HST_MODE(musb);
}
#ifdef CONFIG_PM
if (!(devctl & MUSB_DEVCTL_SESSION))
stm_musb_context(USB_DISABLE);
#endif
break;
case OTG_STATE_A_SUSPEND:
default:
break;
}
stm_set_peripheral_clock(PERI5_CLK_DISABLE);
spin_unlock_irqrestore(&musb->lock, flags);
DBG(1, "otg_state %s devctl %d\n", otg_state_string(musb),
devctl);
}
}
void musb_root_disconnect(struct musb *musb)
{
musb->port1_status = (1 << USB_PORT_FEAT_POWER)
| (1 << USB_PORT_FEAT_C_CONNECTION);
usb_hcd_poll_rh_status(musb_to_hcd(musb));
musb->is_active = 0;
switch (musb->xceiv->state) {
case OTG_STATE_A_HOST:
case OTG_STATE_A_SUSPEND:
musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
musb->is_active = 0;
break;
case OTG_STATE_A_WAIT_VFALL:
musb->xceiv->state = OTG_STATE_B_IDLE;
break;
default:
DBG(1, "host disconnect (%s)\n", otg_state_string(musb));
}
}
static void otg_timer(unsigned long _musb)
{
struct musb *musb = (void *)_musb;
void __iomem *mregs = musb->mregs;
u8 devctl;
unsigned long flags;
devctl = musb_readb(mregs, MUSB_DEVCTL);
dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
case OTG_STATE_A_WAIT_VFALL:
if (devctl & MUSB_DEVCTL_VBUS) {
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
break;
}
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
break;
case OTG_STATE_B_IDLE:
if (!is_peripheral_enabled(musb))
break;
musb_writeb(mregs, MUSB_DEVCTL,
devctl | MUSB_DEVCTL_SESSION);
devctl = musb_readb(mregs, MUSB_DEVCTL);
if (devctl & MUSB_DEVCTL_BDEVICE)
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
else
musb->xceiv->state = OTG_STATE_A_IDLE;
break;
default:
break;
}
spin_unlock_irqrestore(&musb->lock, flags);
}
static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
{
unsigned long flags;
irqreturn_t retval = IRQ_NONE;
struct musb *musb = __hci;
void __iomem *tibase = musb->ctrl_base;
struct cppi *cppi;
u32 tmp;
spin_lock_irqsave(&musb->lock, flags);
/* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
* the Mentor registers (except for setup), use the TI ones and EOI.
*
* Docs describe irq "vector" registers associated with the CPPI and
* USB EOI registers. These hold a bitmask corresponding to the
* current IRQ, not an irq handler address. Would using those bits
* resolve some of the races observed in this dispatch code??
*/
/* CPPI interrupts share the same IRQ line, but have their own
* mask, state, "vector", and EOI registers.
*/
cppi = container_of(musb->dma_controller, struct cppi, controller);
if (is_cppi_enabled(musb) && musb->dma_controller && !cppi->irq)
retval = cppi_interrupt(irq, __hci);
/* ack and handle non-CPPI interrupts */
tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
DBG(4, "IRQ %08x\n", tmp);
musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
>> DAVINCI_USB_RXINT_SHIFT;
musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
>> DAVINCI_USB_TXINT_SHIFT;
musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
>> DAVINCI_USB_USBINT_SHIFT;
/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
* DaVinci's missing ID change IRQ. We need an ID change IRQ to
* switch appropriately between halves of the OTG state machine.
* Managing DEVCTL.SESSION per Mentor docs requires we know its
* value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
* Also, DRVVBUS pulses for SRP (but not at 5V) ...
*/
if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
void __iomem *mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
int err = musb->int_usb & MUSB_INTR_VBUSERROR;
err = is_host_enabled(musb)
&& (musb->int_usb & MUSB_INTR_VBUSERROR);
if (err) {
/* The Mentor core doesn't debounce VBUS as needed
* to cope with device connect current spikes. This
* means it's not uncommon for bus-powered devices
* to get VBUS errors during enumeration.
*
* This is a workaround, but newer RTL from Mentor
* seems to allow a better one: "re"starting sessions
* without waiting (on EVM, a **long** time) for VBUS
* to stop registering in devctl.
*/
musb->int_usb &= ~MUSB_INTR_VBUSERROR;
musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
WARNING("VBUS error workaround (delay coming)\n");
} else if (is_host_enabled(musb) && drvvbus) {
MUSB_HST_MODE(musb);
musb->xceiv->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
portstate(musb->port1_status |= USB_PORT_STAT_POWER);
del_timer(&otg_workaround);
} else {
musb->is_active = 0;
MUSB_DEV_MODE(musb);
musb->xceiv->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
}
/* NOTE: this must complete poweron within 100 msec
* (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
*/
davinci_musb_source_power(musb, drvvbus, 0);
DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb),
err ? " ERROR" : "",
devctl);
retval = IRQ_HANDLED;
}
if (musb->int_tx || musb->int_rx || musb->int_usb)
retval |= musb_interrupt(musb);
/* irq stays asserted until EOI is written */
musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
/* poll for ID change */
if (is_otg_enabled(musb)
&& musb->xceiv->state == OTG_STATE_B_IDLE)
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
spin_unlock_irqrestore(&musb->lock, flags);
return retval;
}
static void musb_port_suspend(struct musb *musb, bool do_suspend)
{
u8 power;
void __iomem *mbase = musb->mregs;
struct device *dev = musb->controller;
struct musb_hdrc_platform_data *plat = dev->platform_data;
struct omap_musb_board_data *data = plat->board_data;
if (!is_host_active(musb))
return;
/* NOTE: this doesn't necessarily put PHY into low power mode,
* turning off its clock; that's a function of PHY integration and
* MUSB_POWER_ENSUSPEND. PHY may need a clock (sigh) to detect
* SE0 changing to connect (J) or wakeup (K) states.
*/
power = musb_readb(mbase, MUSB_POWER);
if (do_suspend) {
int retries = 10000;
power &= ~MUSB_POWER_RESUME;
power |= MUSB_POWER_SUSPENDM;
if (data->interface_type == MUSB_INTERFACE_UTMI)
power |= MUSB_POWER_ENSUSPEND;
musb_writeb(mbase, MUSB_POWER, power);
/* Needed for OPT A tests */
power = musb_readb(mbase, MUSB_POWER);
while (power & MUSB_POWER_SUSPENDM) {
power = musb_readb(mbase, MUSB_POWER);
if (retries-- < 1)
break;
}
DBG(3, "Root port suspended, power %02x\n", power);
musb->port1_status |= USB_PORT_STAT_SUSPEND;
switch (musb->xceiv->state) {
case OTG_STATE_A_HOST:
musb->xceiv->state = OTG_STATE_A_SUSPEND;
musb->is_active = is_otg_enabled(musb)
&& musb->xceiv->host->b_hnp_enable;
if (musb->is_active)
mod_timer(&musb->otg_timer, jiffies
+ msecs_to_jiffies(
OTG_TIME_A_AIDL_BDIS));
musb_platform_try_idle(musb, 0);
/*
* disable the phy clock when the device is supended.
* this will allow the core retention
*/
otg_set_clk(musb->xceiv, 0);
break;
#ifdef CONFIG_USB_MUSB_OTG
case OTG_STATE_B_HOST:
musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
musb->is_active = is_otg_enabled(musb)
&& musb->xceiv->host->b_hnp_enable;
musb_platform_try_idle(musb, 0);
break;
#endif
default:
DBG(1, "bogus rh suspend? %s\n",
otg_state_string(musb));
}
} else if (power & MUSB_POWER_SUSPENDM) {
power &= ~MUSB_POWER_SUSPENDM;
if (data->interface_type == MUSB_INTERFACE_UTMI)
power &= ~MUSB_POWER_ENSUSPEND;
power |= MUSB_POWER_RESUME;
musb_writeb(mbase, MUSB_POWER, power);
otg_set_clk(musb->xceiv, 1);
DBG(3, "Root port resuming, power %02x\n", power);
/* later, GetPortStatus will stop RESUME signaling */
musb->port1_status |= MUSB_PORT_STAT_RESUME;
musb->rh_timer = jiffies + msecs_to_jiffies(20);
}
}
static irqreturn_t dsps_interrupt(int irq, void *hci)
{
struct musb *musb = hci;
void __iomem *reg_base = musb->ctrl_base;
struct device *dev = musb->controller;
struct platform_device *pdev = to_platform_device(dev);
struct dsps_glue *glue = dev_get_drvdata(dev->parent);
const struct dsps_musb_wrapper *wrp = glue->wrp;
unsigned long flags;
irqreturn_t ret = IRQ_NONE;
u32 epintr, usbintr;
spin_lock_irqsave(&musb->lock, flags);
/* Get endpoint interrupts */
epintr = dsps_readl(reg_base, wrp->epintr_status);
musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
if (epintr)
dsps_writel(reg_base, wrp->epintr_status, epintr);
/* Get usb core interrupts */
usbintr = dsps_readl(reg_base, wrp->coreintr_status);
if (!usbintr && !epintr)
goto eoi;
musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
if (usbintr)
dsps_writel(reg_base, wrp->coreintr_status, usbintr);
dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
usbintr, epintr);
/*
* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
* DSPS IP's missing ID change IRQ. We need an ID change IRQ to
* switch appropriately between halves of the OTG state machine.
* Managing DEVCTL.SESSION per Mentor docs requires that we know its
* value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
* Also, DRVVBUS pulses for SRP (but not at 5V) ...
*/
if (usbintr & MUSB_INTR_BABBLE)
pr_info("CAUTION: musb: Babble Interrupt Occured\n");
if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
int drvvbus = dsps_readl(reg_base, wrp->status);
void __iomem *mregs = musb->mregs;
u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);
int err;
err = musb->int_usb & MUSB_INTR_VBUSERROR;
if (err) {
/*
* The Mentor core doesn't debounce VBUS as needed
* to cope with device connect current spikes. This
* means it's not uncommon for bus-powered devices
* to get VBUS errors during enumeration.
*
* This is a workaround, but newer RTL from Mentor
* seems to allow a better one: "re"-starting sessions
* without waiting for VBUS to stop registering in
* devctl.
*/
musb->int_usb &= ~MUSB_INTR_VBUSERROR;
musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
mod_timer(&glue->timer[pdev->id],
jiffies + wrp->poll_seconds * HZ);
WARNING("VBUS error workaround (delay coming)\n");
} else if (drvvbus) {
musb->is_active = 1;
MUSB_HST_MODE(musb);
musb->xceiv->otg->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
del_timer(&glue->timer[pdev->id]);
} else {
musb->is_active = 0;
MUSB_DEV_MODE(musb);
musb->xceiv->otg->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
}
/* NOTE: this must complete power-on within 100 ms. */
dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
devctl);
ret = IRQ_HANDLED;
}
if (musb->int_tx || musb->int_rx || musb->int_usb)
ret |= musb_interrupt(musb);
eoi:
/* EOI needs to be written for the IRQ to be re-asserted. */
if (ret == IRQ_HANDLED || epintr || usbintr)
dsps_writel(reg_base, wrp->eoi, 1);
/* Poll for ID change */
if (musb->xceiv->state == OTG_STATE_B_IDLE)
mod_timer(&glue->timer[pdev->id],
jiffies + wrp->poll_seconds * HZ);
spin_unlock_irqrestore(&musb->lock, flags);
return ret;
}
static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
{
struct musb *musb = hci;
void __iomem *reg_base = musb->ctrl_base;
struct usb_otg *otg = musb->xceiv->otg;
unsigned long flags;
irqreturn_t ret = IRQ_NONE;
u32 status;
spin_lock_irqsave(&musb->lock, flags);
/*
* NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
* the Mentor registers (except for setup), use the TI ones and EOI.
*/
/* Acknowledge and handle non-CPPI interrupts */
status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
if (!status)
goto eoi;
musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
dev_dbg(musb->controller, "USB IRQ %08x\n", status);
musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
/*
* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
* DA8xx's missing ID change IRQ. We need an ID change IRQ to
* switch appropriately between halves of the OTG state machine.
* Managing DEVCTL.Session per Mentor docs requires that we know its
* value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
* Also, DRVVBUS pulses for SRP (but not at 5 V)...
*/
if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
void __iomem *mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
int err;
err = is_host_enabled(musb) && (musb->int_usb &
MUSB_INTR_VBUSERROR);
if (err) {
/*
* The Mentor core doesn't debounce VBUS as needed
* to cope with device connect current spikes. This
* means it's not uncommon for bus-powered devices
* to get VBUS errors during enumeration.
*
* This is a workaround, but newer RTL from Mentor
* seems to allow a better one: "re"-starting sessions
* without waiting for VBUS to stop registering in
* devctl.
*/
musb->int_usb &= ~MUSB_INTR_VBUSERROR;
musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
WARNING("VBUS error workaround (delay coming)\n");
} else if (is_host_enabled(musb) && drvvbus) {
MUSB_HST_MODE(musb);
otg->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
portstate(musb->port1_status |= USB_PORT_STAT_POWER);
del_timer(&otg_workaround);
} else {
musb->is_active = 0;
MUSB_DEV_MODE(musb);
otg->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
}
dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
devctl);
ret = IRQ_HANDLED;
}
if (musb->int_tx || musb->int_rx || musb->int_usb)
ret |= musb_interrupt(musb);
eoi:
/* EOI needs to be written for the IRQ to be re-asserted. */
if (ret == IRQ_HANDLED || status)
musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
/* Poll for ID change */
if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
spin_unlock_irqrestore(&musb->lock, flags);
return ret;
}
/**
* dwc3_otg_sm_work - workqueue function.
*
* @w: Pointer to the dwc3 otg workqueue
*
* NOTE: After any change in phy->state,
* we must reschdule the state machine.
*/
static void dwc3_otg_sm_work(struct work_struct *w)
{
struct dwc3_otg *dotg = container_of(w, struct dwc3_otg, sm_work.work);
struct usb_phy *phy = dotg->otg.phy;
struct dwc3_charger *charger = dotg->charger;
bool work = 0;
int ret = 0;
unsigned long delay = 0;
pm_runtime_resume(phy->dev);
dev_dbg(phy->dev, "%s state\n", otg_state_string(phy->state));
/* Check OTG state */
switch (phy->state) {
case OTG_STATE_UNDEFINED:
dwc3_otg_init_sm(dotg);
if (!dotg->psy) {
dotg->psy = power_supply_get_by_name("usb");
if (!dotg->psy)
dev_err(phy->dev,
"couldn't get usb power supply\n");
}
/* Switch to A or B-Device according to ID / BSV */
if (!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id\n");
phy->state = OTG_STATE_A_IDLE;
work = 1;
} else if (test_bit(B_SESS_VLD, &dotg->inputs)) {
dev_dbg(phy->dev, "b_sess_vld\n");
phy->state = OTG_STATE_B_IDLE;
work = 1;
} else {
phy->state = OTG_STATE_B_IDLE;
dev_dbg(phy->dev, "No device, trying to suspend\n");
pm_runtime_put_sync(phy->dev);
}
break;
case OTG_STATE_B_IDLE:
if (!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id\n");
phy->state = OTG_STATE_A_IDLE;
work = 1;
dotg->charger_retry_count = 0;
if (charger) {
if (charger->chg_type == DWC3_INVALID_CHARGER)
charger->start_detection(dotg->charger,
false);
else
charger->chg_type =
DWC3_INVALID_CHARGER;
}
} else if (test_bit(B_SESS_VLD, &dotg->inputs)) {
dev_dbg(phy->dev, "b_sess_vld\n");
if (charger) {
/* Has charger been detected? If no detect it */
switch (charger->chg_type) {
case DWC3_DCP_CHARGER:
case DWC3_PROPRIETARY_CHARGER:
dev_dbg(phy->dev, "lpm, DCP charger\n");
dwc3_otg_set_power(phy,
DWC3_IDEV_CHG_MAX);
pm_runtime_put_sync(phy->dev);
break;
case DWC3_CDP_CHARGER:
dwc3_otg_set_power(phy,
DWC3_IDEV_CHG_MAX);
dwc3_otg_start_peripheral(&dotg->otg,
1);
phy->state = OTG_STATE_B_PERIPHERAL;
work = 1;
break;
case DWC3_SDP_CHARGER:
dwc3_otg_start_peripheral(&dotg->otg,
1);
phy->state = OTG_STATE_B_PERIPHERAL;
work = 1;
/* OPPO 2013-10-05 wangjc Add begin for support non-standard charger, HW_VERSION__12 is dvt */
#ifdef CONFIG_MACH_MSM8974_14001
#if defined(CONFIG_OPPO_DEVICE_FIND7) || defined(CONFIG_OPPO_DEVICE_FIND7WX)
if(get_pcb_version() < HW_VERSION__12) {
cancel_delayed_work_sync(&dotg->non_standard_charger_work);
non_standard = true;
schedule_delayed_work(&dotg->non_standard_charger_work,
round_jiffies_relative(msecs_to_jiffies
(5000)));
} else {
/* [email protected], 2014/01/23 Add for notify usb online earlier */
power_supply_set_online(dotg->psy, true);
power_supply_changed(dotg->psy);
}
#else
power_supply_set_online(dotg->psy, true);
power_supply_changed(dotg->psy);
#endif
#endif
/* OPPO 2013-10-05 wangjc Add end */
break;
case DWC3_FLOATED_CHARGER:
/* OPPO 2013-10-05 wangjc Modify begin for support non-standard charger */
#ifndef CONFIG_MACH_MSM8974_14001
if (dotg->charger_retry_count <
max_chgr_retry_count)
dotg->charger_retry_count++;
/*
* In case of floating charger, if
* retry count equal to max retry count
* notify PMIC about floating charger
* and put Hw in low power mode. Else
* perform charger detection again by
* calling start_detection() with false
* and then with true argument.
*/
if (dotg->charger_retry_count ==
max_chgr_retry_count) {
dwc3_otg_set_power(phy, 0);
pm_runtime_put_sync(phy->dev);
break;
}
charger->start_detection(dotg->charger,
false);
#else
dev_dbg(phy->dev, "lpm, FLOATED charger\n");
dwc3_otg_set_power(phy,
DWC3_IDEV_CHG_FLOATED);
pm_runtime_put_sync(phy->dev);
break;
#endif
/* OPPO 2013-10-05 wangjc Modify end */
default:
dev_dbg(phy->dev, "chg_det started\n");
/* OPPO 2013-11-18 wangjc Modify begin for detect charger type later */
#ifndef CONFIG_MACH_MSM8974_14001
charger->start_detection(charger, true);
#else
/* [email protected], 2014/02/24 Add for solve usb reboot problem */
cancel_delayed_work_sync(&dotg->detect_work);
/* [email protected], 2014/03/25 Add for solve usb reboot problem,bug 422328 */
if (charger)
charger->start_detection(dotg->charger, false);
dotg->charger_retry_count = 0;
dwc3_otg_set_power(phy, 0);
queue_delayed_work(system_nrt_wq, &dotg->detect_work, msecs_to_jiffies(600));
#endif
/* OPPO 2013-11-18 wangjc Modify end */
break;
}
} else {
/* no charger registered, start peripheral */
if (dwc3_otg_start_peripheral(&dotg->otg, 1)) {
/*
* Probably set_peripheral not called
* yet. We will re-try as soon as it
* will be called
*/
dev_err(phy->dev, "enter lpm as\n"
"unable to start B-device\n");
phy->state = OTG_STATE_UNDEFINED;
pm_runtime_put_sync(phy->dev);
return;
}
}
} else {
/* OPPO 2013-12-01 wangjc Add begin for for non standard charger detect, HW_VERSION__12 is dvt */
#ifdef CONFIG_MACH_MSM8974_14001
//#ifdef CONFIG_OPPO_DEVICE_FIND7
#if defined(CONFIG_OPPO_DEVICE_FIND7) || defined(CONFIG_OPPO_DEVICE_FIND7WX)
if(get_pcb_version() < HW_VERSION__12) {
cancel_delayed_work_sync(&dotg->non_standard_charger_work);
}
#endif
#endif
/* OPPO 2013-12-01 wangjc Add end */
#ifdef CONFIG_MACH_MSM8974_14001
/* [email protected], 2014/01/06 Add for solve usb reboot problem */
cancel_delayed_work_sync(&dotg->detect_work);
#endif /*CONFIG_MACH_MSM8974_14001*/
if (charger)
charger->start_detection(dotg->charger, false);
dotg->charger_retry_count = 0;
dwc3_otg_set_power(phy, 0);
dev_dbg(phy->dev, "No device, trying to suspend\n");
pm_runtime_put_sync(phy->dev);
}
break;
case OTG_STATE_B_PERIPHERAL:
if (!test_bit(B_SESS_VLD, &dotg->inputs) ||
!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id || !bsv\n");
dwc3_otg_start_peripheral(&dotg->otg, 0);
phy->state = OTG_STATE_B_IDLE;
if (charger)
charger->chg_type = DWC3_INVALID_CHARGER;
work = 1;
}
break;
case OTG_STATE_A_IDLE:
/* Switch to A-Device*/
if (test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "id\n");
phy->state = OTG_STATE_B_IDLE;
dotg->vbus_retry_count = 0;
work = 1;
} else {
phy->state = OTG_STATE_A_HOST;
ret = dwc3_otg_start_host(&dotg->otg, 1);
if ((ret == -EPROBE_DEFER) &&
dotg->vbus_retry_count < 3) {
/*
* Get regulator failed as regulator driver is
* not up yet. Will try to start host after 1sec
*/
phy->state = OTG_STATE_A_IDLE;
dev_dbg(phy->dev, "Unable to get vbus regulator. Retrying...\n");
delay = VBUS_REG_CHECK_DELAY;
work = 1;
dotg->vbus_retry_count++;
} else if (ret) {
/*
* Probably set_host was not called yet.
* We will re-try as soon as it will be called
*/
dev_dbg(phy->dev, "enter lpm as\n"
"unable to start A-device\n");
phy->state = OTG_STATE_A_IDLE;
pm_runtime_put_sync(phy->dev);
return;
}
}
break;
case OTG_STATE_A_HOST:
if (test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "id\n");
dwc3_otg_start_host(&dotg->otg, 0);
phy->state = OTG_STATE_B_IDLE;
dotg->vbus_retry_count = 0;
work = 1;
}
break;
default:
dev_err(phy->dev, "%s: invalid otg-state\n", __func__);
}
if (work)
queue_delayed_work(system_nrt_wq, &dotg->sm_work, delay);
}
static void isp_update_otg(struct isp1301 *isp, u8 stat)
{
u8 isp_stat, isp_bstat;
enum usb_otg_state state = isp->otg.state;
if (stat & INTR_BDIS_ACON)
pr_debug("OTG: BDIS_ACON, %s\n", state_name(isp));
/* start certain state transitions right away */
isp_stat = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
if (isp_stat & INTR_ID_GND) {
if (isp->otg.default_a) {
switch (state) {
case OTG_STATE_B_IDLE:
a_idle(isp, "idle");
/* FALLTHROUGH */
case OTG_STATE_A_IDLE:
enable_vbus_source(isp);
/* FALLTHROUGH */
case OTG_STATE_A_WAIT_VRISE:
/* we skip over OTG_STATE_A_WAIT_BCON, since
* the HC will transition to A_HOST (or
* A_SUSPEND!) without our noticing except
* when HNP is used.
*/
if (isp_stat & INTR_VBUS_VLD)
isp->otg.state = OTG_STATE_A_HOST;
break;
case OTG_STATE_A_WAIT_VFALL:
if (!(isp_stat & INTR_SESS_VLD))
a_idle(isp, "vfell");
break;
default:
if (!(isp_stat & INTR_VBUS_VLD))
isp->otg.state = OTG_STATE_A_VBUS_ERR;
break;
}
isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
} else {
switch (state) {
case OTG_STATE_B_PERIPHERAL:
case OTG_STATE_B_HOST:
case OTG_STATE_B_WAIT_ACON:
usb_gadget_vbus_disconnect(isp->otg.gadget);
break;
default:
break;
}
if (state != OTG_STATE_A_IDLE)
a_idle(isp, "id");
if (isp->otg.host && state == OTG_STATE_A_IDLE)
isp1301_defer_work(isp, WORK_HOST_RESUME);
isp_bstat = 0;
}
} else {
u32 l;
/* if user unplugged mini-A end of cable,
* don't bypass A_WAIT_VFALL.
*/
if (isp->otg.default_a) {
switch (state) {
default:
isp->otg.state = OTG_STATE_A_WAIT_VFALL;
break;
case OTG_STATE_A_WAIT_VFALL:
state = OTG_STATE_A_IDLE;
/* khubd may take a while to notice and
* handle this disconnect, so don't go
* to B_IDLE quite yet.
*/
break;
case OTG_STATE_A_IDLE:
host_suspend(isp);
isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1,
MC1_BDIS_ACON_EN);
isp->otg.state = OTG_STATE_B_IDLE;
l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
l &= ~OTG_CTRL_BITS;
omap_writel(l, OTG_CTRL);
break;
case OTG_STATE_B_IDLE:
break;
}
}
isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
switch (isp->otg.state) {
case OTG_STATE_B_PERIPHERAL:
case OTG_STATE_B_WAIT_ACON:
case OTG_STATE_B_HOST:
if (likely(isp_bstat & OTG_B_SESS_VLD))
break;
enable_vbus_draw(isp, 0);
#ifndef CONFIG_USB_OTG
/* UDC driver will clear OTG_BSESSVLD */
isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1,
OTG1_DP_PULLDOWN);
isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1,
OTG1_DP_PULLUP);
dump_regs(isp, __func__);
#endif
/* FALLTHROUGH */
case OTG_STATE_B_SRP_INIT:
b_idle(isp, __func__);
l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
omap_writel(l, OTG_CTRL);
/* FALLTHROUGH */
case OTG_STATE_B_IDLE:
if (isp->otg.gadget && (isp_bstat & OTG_B_SESS_VLD)) {
#ifdef CONFIG_USB_OTG
update_otg1(isp, isp_stat);
update_otg2(isp, isp_bstat);
#endif
b_peripheral(isp);
} else if (!(isp_stat & (INTR_VBUS_VLD|INTR_SESS_VLD)))
isp_bstat |= OTG_B_SESS_END;
break;
case OTG_STATE_A_WAIT_VFALL:
break;
default:
pr_debug("otg: unsupported b-device %s\n",
state_name(isp));
break;
}
}
if (state != isp->otg.state)
pr_debug(" isp, %s -> %s\n",
otg_state_string(state), state_name(isp));
#ifdef CONFIG_USB_OTG
/* update the OTG controller state to match the isp1301; may
* trigger OPRT_CHG irqs for changes going to the isp1301.
*/
update_otg1(isp, isp_stat);
update_otg2(isp, isp_bstat);
check_state(isp, __func__);
#endif
dump_regs(isp, "isp1301->otg");
}
/**
* dwc3_otg_sm_work - workqueue function.
*
* @w: Pointer to the dwc3 otg workqueue
*
* NOTE: After any change in phy->state,
* we must reschdule the state machine.
*/
static void dwc3_otg_sm_work(struct work_struct *w)
{
struct dwc3_otg *dotg = container_of(w, struct dwc3_otg, sm_work.work);
struct usb_phy *phy = dotg->otg.phy;
struct dwc3_charger *charger = dotg->charger;
bool work = 0;
int ret = 0;
unsigned long delay = 0;
pm_runtime_resume(phy->dev);
dev_dbg(phy->dev, "%s state\n", otg_state_string(phy->state));
/* Check OTG state */
switch (phy->state) {
case OTG_STATE_UNDEFINED:
dwc3_otg_init_sm(dotg);
if (!dotg->psy) {
dotg->psy = power_supply_get_by_name("usb");
if (!dotg->psy)
dev_err(phy->dev,
"couldn't get usb power supply\n");
}
/* Switch to A or B-Device according to ID / BSV */
if (!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id\n");
phy->state = OTG_STATE_A_IDLE;
work = 1;
} else if (test_bit(B_SESS_VLD, &dotg->inputs)) {
dev_dbg(phy->dev, "b_sess_vld\n");
phy->state = OTG_STATE_B_IDLE;
work = 1;
} else {
phy->state = OTG_STATE_B_IDLE;
dev_dbg(phy->dev, "No device, trying to suspend\n");
pm_runtime_put_sync(phy->dev);
}
break;
case OTG_STATE_B_IDLE:
if (!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id\n");
phy->state = OTG_STATE_A_IDLE;
work = 1;
dotg->charger_retry_count = 0;
if (charger) {
if (charger->chg_type == DWC3_INVALID_CHARGER)
charger->start_detection(dotg->charger,
false);
else
charger->chg_type =
DWC3_INVALID_CHARGER;
}
} else if (test_bit(B_SESS_VLD, &dotg->inputs)) {
dev_dbg(phy->dev, "b_sess_vld\n");
if (charger) {
/* Has charger been detected? If no detect it */
switch (charger->chg_type) {
case DWC3_DCP_CHARGER:
case DWC3_PROPRIETARY_CHARGER:
dev_dbg(phy->dev, "lpm, DCP charger\n");
dwc3_otg_set_power(phy,
DWC3_IDEV_CHG_MAX);
pm_runtime_put_sync(phy->dev);
break;
case DWC3_CDP_CHARGER:
dwc3_otg_set_power(phy,
DWC3_IDEV_CHG_MAX);
dwc3_otg_start_peripheral(&dotg->otg,
1);
phy->state = OTG_STATE_B_PERIPHERAL;
work = 1;
break;
case DWC3_SDP_CHARGER:
dwc3_otg_start_peripheral(&dotg->otg,
1);
phy->state = OTG_STATE_B_PERIPHERAL;
work = 1;
break;
case DWC3_FLOATED_CHARGER:
#ifdef CONFIG_ZTEMT_COMM_CHARGE
dev_dbg(phy->dev, "lpm, FLOATED charger\n");
dwc3_otg_set_power(phy,
DWC3_IDEV_CHG_MAX);
pm_runtime_put_sync(phy->dev);
#else
if (dotg->charger_retry_count <
max_chgr_retry_count)
dotg->charger_retry_count++;
/*
* In case of floating charger, if
* retry count equal to max retry count
* notify PMIC about floating charger
* and put Hw in low power mode. Else
* perform charger detection again by
* calling start_detection() with false
* and then with true argument.
*/
if (dotg->charger_retry_count ==
max_chgr_retry_count) {
dwc3_otg_set_power(phy, 0);
pm_runtime_put_sync(phy->dev);
break;
}
charger->start_detection(dotg->charger,
false);
#endif
default:
dev_dbg(phy->dev, "chg_det started\n");
charger->start_detection(charger, true);
break;
}
} else {
/* no charger registered, start peripheral */
if (dwc3_otg_start_peripheral(&dotg->otg, 1)) {
/*
* Probably set_peripheral not called
* yet. We will re-try as soon as it
* will be called
*/
dev_err(phy->dev, "enter lpm as\n"
"unable to start B-device\n");
phy->state = OTG_STATE_UNDEFINED;
pm_runtime_put_sync(phy->dev);
return;
}
}
} else {
if (charger)
charger->start_detection(dotg->charger, false);
dotg->charger_retry_count = 0;
dwc3_otg_set_power(phy, 0);
dev_dbg(phy->dev, "No device, trying to suspend\n");
pm_runtime_put_sync(phy->dev);
}
break;
case OTG_STATE_B_PERIPHERAL:
if (!test_bit(B_SESS_VLD, &dotg->inputs) ||
!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id || !bsv\n");
dwc3_otg_start_peripheral(&dotg->otg, 0);
phy->state = OTG_STATE_B_IDLE;
if (charger)
charger->chg_type = DWC3_INVALID_CHARGER;
work = 1;
}
break;
case OTG_STATE_A_IDLE:
/* Switch to A-Device*/
if (test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "id\n");
phy->state = OTG_STATE_B_IDLE;
dotg->vbus_retry_count = 0;
work = 1;
} else {
phy->state = OTG_STATE_A_HOST;
ret = dwc3_otg_start_host(&dotg->otg, 1);
if ((ret == -EPROBE_DEFER) &&
dotg->vbus_retry_count < 3) {
/*
* Get regulator failed as regulator driver is
* not up yet. Will try to start host after 1sec
*/
phy->state = OTG_STATE_A_IDLE;
dev_dbg(phy->dev, "Unable to get vbus regulator. Retrying...\n");
delay = VBUS_REG_CHECK_DELAY;
work = 1;
dotg->vbus_retry_count++;
} else if (ret) {
/*
* Probably set_host was not called yet.
* We will re-try as soon as it will be called
*/
dev_dbg(phy->dev, "enter lpm as\n"
"unable to start A-device\n");
phy->state = OTG_STATE_A_IDLE;
pm_runtime_put_sync(phy->dev);
return;
}
}
break;
case OTG_STATE_A_HOST:
if (test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "id\n");
dwc3_otg_start_host(&dotg->otg, 0);
phy->state = OTG_STATE_B_IDLE;
dotg->vbus_retry_count = 0;
work = 1;
}
break;
default:
dev_err(phy->dev, "%s: invalid otg-state\n", __func__);
}
if (work)
queue_delayed_work(system_nrt_wq, &dotg->sm_work, delay);
}
static void check_state(struct isp1301 *isp, const char *tag)
{
enum usb_otg_state state = OTG_STATE_UNDEFINED;
u8 fsm = omap_readw(OTG_TEST) & 0x0ff;
unsigned extra = 0;
switch (fsm) {
/* default-b */
case 0x0:
state = OTG_STATE_B_IDLE;
break;
case 0x3:
case 0x7:
extra = 1;
case 0x1:
state = OTG_STATE_B_PERIPHERAL;
break;
case 0x11:
state = OTG_STATE_B_SRP_INIT;
break;
/* extra dual-role default-b states */
case 0x12:
case 0x13:
case 0x16:
extra = 1;
case 0x17:
state = OTG_STATE_B_WAIT_ACON;
break;
case 0x34:
state = OTG_STATE_B_HOST;
break;
/* default-a */
case 0x36:
state = OTG_STATE_A_IDLE;
break;
case 0x3c:
state = OTG_STATE_A_WAIT_VFALL;
break;
case 0x7d:
state = OTG_STATE_A_VBUS_ERR;
break;
case 0x9e:
case 0x9f:
extra = 1;
case 0x89:
state = OTG_STATE_A_PERIPHERAL;
break;
case 0xb7:
state = OTG_STATE_A_WAIT_VRISE;
break;
case 0xb8:
state = OTG_STATE_A_WAIT_BCON;
break;
case 0xb9:
state = OTG_STATE_A_HOST;
break;
case 0xba:
state = OTG_STATE_A_SUSPEND;
break;
default:
break;
}
if (isp->otg.state == state && !extra)
return;
pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag,
otg_state_string(state), fsm, state_name(isp),
omap_readl(OTG_CTRL));
}
static inline const char *state_name(struct isp1301 *isp)
{
return otg_state_string(isp->otg.state);
}
static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
{
struct musb *musb = hci;
void __iomem *reg_base = musb->ctrl_base;
struct device *dev = musb->controller;
struct musb_hdrc_platform_data *plat = dev->platform_data;
struct omap_musb_board_data *data = plat->board_data;
unsigned long flags;
irqreturn_t ret = IRQ_NONE;
u32 epintr, usbintr;
spin_lock_irqsave(&musb->lock, flags);
/* Get endpoint interrupts */
epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
if (epintr) {
musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
musb->int_rx =
(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
musb->int_tx =
(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
}
/* Get usb core interrupts */
usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
if (!usbintr && !epintr)
goto eoi;
if (usbintr) {
musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
musb->int_usb =
(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
}
/*
* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
* AM35x's missing ID change IRQ. We need an ID change IRQ to
* switch appropriately between halves of the OTG state machine.
* Managing DEVCTL.SESSION per Mentor docs requires that we know its
* value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
* Also, DRVVBUS pulses for SRP (but not at 5V) ...
*/
if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
int drvvbus = musb_readl(reg_base, USB_STAT_REG);
void __iomem *mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
int err;
err = is_host_enabled(musb) && (musb->int_usb &
MUSB_INTR_VBUSERROR);
if (err) {
/*
* The Mentor core doesn't debounce VBUS as needed
* to cope with device connect current spikes. This
* means it's not uncommon for bus-powered devices
* to get VBUS errors during enumeration.
*
* This is a workaround, but newer RTL from Mentor
* seems to allow a better one: "re"-starting sessions
* without waiting for VBUS to stop registering in
* devctl.
*/
musb->int_usb &= ~MUSB_INTR_VBUSERROR;
musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
WARNING("VBUS error workaround (delay coming)\n");
} else if (is_host_enabled(musb) && drvvbus) {
MUSB_HST_MODE(musb);
musb->xceiv->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
portstate(musb->port1_status |= USB_PORT_STAT_POWER);
del_timer(&otg_workaround);
} else {
musb->is_active = 0;
MUSB_DEV_MODE(musb);
musb->xceiv->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
}
/* NOTE: this must complete power-on within 100 ms. */
dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
devctl);
ret = IRQ_HANDLED;
}
/* Drop spurious RX and TX if device is disconnected */
if (musb->int_usb & MUSB_INTR_DISCONNECT) {
musb->int_tx = 0;
musb->int_rx = 0;
}
if (musb->int_tx || musb->int_rx || musb->int_usb)
ret |= musb_interrupt(musb);
eoi:
/* EOI needs to be written for the IRQ to be re-asserted. */
if (ret == IRQ_HANDLED || epintr || usbintr) {
/* clear level interrupt */
if (data->clear_irq)
data->clear_irq();
/* write EOI */
musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
}
/* Poll for ID change */
if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
spin_unlock_irqrestore(&musb->lock, flags);
return ret;
}
static void musb_port_suspend(struct musb *musb, bool do_suspend)
{
u8 power;
void __iomem *mbase = musb->mregs;
if (!is_host_enabled(musb))
return;
/* NOTE: this doesn't necessarily put PHY into low power mode,
* turning off its clock; that's a function of PHY integration and
* MUSB_POWER_ENSUSPEND. PHY may need a clock (sigh) to detect
* SE0 changing to connect (J) or wakeup (K) states.
*/
power = musb_readb(mbase, MUSB_POWER);
if (do_suspend) {
int retries = 10000;
power &= ~MUSB_POWER_RESUME;
power |= MUSB_POWER_SUSPENDM;
musb_writeb(mbase, MUSB_POWER, power);
/* Needed for OPT A tests */
power = musb_readb(mbase, MUSB_POWER);
while (power & MUSB_POWER_SUSPENDM) {
power = musb_readb(mbase, MUSB_POWER);
if (retries-- < 1)
break;
}
dev_dbg(musb->controller, "Root port suspended, power %02x\n", power);
musb->port1_status |= USB_PORT_STAT_SUSPEND;
switch (musb->xceiv->state) {
case OTG_STATE_A_HOST:
musb->xceiv->state = OTG_STATE_A_SUSPEND;
musb->is_active = is_otg_enabled(musb)
&& musb->xceiv->host->b_hnp_enable;
musb_platform_try_idle(musb, 0);
break;
case OTG_STATE_B_HOST:
if (is_otg_enabled(musb)) {
musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
musb->is_active = is_otg_enabled(musb)
&& musb->xceiv->host->b_hnp_enable;
musb_platform_try_idle(musb, 0);
}
break;
default:
dev_dbg(musb->controller, "bogus rh suspend? %s\n",
otg_state_string(musb->xceiv->state));
}
} else if (power & MUSB_POWER_SUSPENDM) {
power &= ~MUSB_POWER_SUSPENDM;
power |= MUSB_POWER_RESUME;
musb_writeb(mbase, MUSB_POWER, power);
dev_dbg(musb->controller, "Root port resuming, power %02x\n", power);
/* later, GetPortStatus will stop RESUME signaling */
musb->port1_status |= MUSB_PORT_STAT_RESUME;
musb->rh_timer = jiffies + msecs_to_jiffies(20);
}
}
/**
* dwc3_otg_sm_work - workqueue function.
*
* @w: Pointer to the dwc3 otg workqueue
*
* NOTE: After any change in phy->state,
* we must reschdule the state machine.
*/
static void dwc3_otg_sm_work(struct work_struct *w)
{
struct dwc3_otg *dotg = container_of(w, struct dwc3_otg, sm_work.work);
struct usb_phy *phy = dotg->otg.phy;
struct dwc3_charger *charger = dotg->charger;
bool work = 0;
int ret = 0;
unsigned long delay = 0;
pm_runtime_resume(phy->dev);
dev_dbg(phy->dev, "%s state\n", otg_state_string(phy->state));
/* Check OTG state */
switch (phy->state) {
case OTG_STATE_UNDEFINED:
dwc3_otg_init_sm(dotg);
if (!dotg->psy) {
dotg->psy = power_supply_get_by_name("usb");
if (!dotg->psy)
dev_err(phy->dev,
"couldn't get usb power supply\n");
}
/* Switch to A or B-Device according to ID / BSV */
if (!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id\n");
phy->state = OTG_STATE_A_IDLE;
work = 1;
} else if (test_bit(B_SESS_VLD, &dotg->inputs)) {
dev_dbg(phy->dev, "b_sess_vld\n");
phy->state = OTG_STATE_B_IDLE;
work = 1;
} else {
phy->state = OTG_STATE_B_IDLE;
dev_dbg(phy->dev, "No device, trying to suspend\n");
pm_runtime_put_sync(phy->dev);
}
break;
case OTG_STATE_B_IDLE:
if (!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id\n");
phy->state = OTG_STATE_A_IDLE;
work = 1;
dotg->charger_retry_count = 0;
if (charger) {
if (charger->chg_type == DWC3_INVALID_CHARGER)
charger->start_detection(dotg->charger,
false);
else
charger->chg_type =
DWC3_INVALID_CHARGER;
}
} else if (test_bit(B_SESS_VLD, &dotg->inputs)) {
dev_dbg(phy->dev, "b_sess_vld\n");
if (charger) {
/* Has charger been detected? If no detect it */
switch (charger->chg_type) {
case DWC3_DCP_CHARGER:
case DWC3_PROPRIETARY_CHARGER:
dev_dbg(phy->dev, "lpm, DCP charger\n");
dwc3_otg_set_power(phy,
DWC3_IDEV_CHG_MAX);
pm_runtime_put_sync(phy->dev);
break;
case DWC3_CDP_CHARGER:
dwc3_otg_set_power(phy,
DWC3_IDEV_CHG_MAX);
dwc3_otg_start_peripheral(&dotg->otg,
1);
phy->state = OTG_STATE_B_PERIPHERAL;
work = 1;
break;
case DWC3_SDP_CHARGER:
dwc3_otg_start_peripheral(&dotg->otg,
1);
phy->state = OTG_STATE_B_PERIPHERAL;
pr_info("DWC3_SDP_CHARGER\n");
work = 1;
break;
case DWC3_FLOATED_CHARGER:
if (dotg->charger_retry_count <
max_chgr_retry_count)
dotg->charger_retry_count++;
/*
* In case of floating charger, if
* retry count equal to max retry count
* notify PMIC about floating charger
* and put Hw in low power mode. Else
* perform charger detection again by
* calling start_detection() with false
* and then with true argument.
*/
if (dotg->charger_retry_count ==
max_chgr_retry_count) {
dwc3_otg_set_power(phy, 0);
pm_runtime_put_sync(phy->dev);
break;
}
charger->start_detection(dotg->charger,
false);
default:
dev_dbg(phy->dev, "chg_det started\n");
charger->start_detection(charger, true);
break;
}
} else {
/* no charger registered, start peripheral */
if (dwc3_otg_start_peripheral(&dotg->otg, 1)) {
/*
* Probably set_peripheral not called
* yet. We will re-try as soon as it
* will be called
*/
dev_err(phy->dev, "enter lpm as\n"
"unable to start B-device\n");
phy->state = OTG_STATE_UNDEFINED;
pm_runtime_put_sync(phy->dev);
return;
}
}
} else {
if (charger)
charger->start_detection(dotg->charger, false);
dotg->charger_retry_count = 0;
dwc3_otg_set_power(phy, 0);
dev_dbg(phy->dev, "No device, trying to suspend\n");
pm_runtime_put_sync(phy->dev);
}
break;
case OTG_STATE_B_PERIPHERAL:
#ifdef CONFIG_PANTECH_USB_BLOCKING_MDMSTATE
if (get_pantech_mdm_state())
dwc3_otg_set_power(phy, DWC3_BLOCKING_USB_MDMSTATE_MAX);
#endif
#ifndef CONFIG_PANTECH_SIO_BUG_FIX
if (!test_bit(B_SESS_VLD, &dotg->inputs) ||
!test_bit(ID, &dotg->inputs)) {
#else
if (!test_bit(B_SESS_VLD, &dotg->inputs)) {
#endif
dev_dbg(phy->dev, "!id || !bsv\n");
dwc3_otg_start_peripheral(&dotg->otg, 0);
phy->state = OTG_STATE_B_IDLE;
if (charger)
charger->chg_type = DWC3_INVALID_CHARGER;
work = 1;
}
break;
case OTG_STATE_A_IDLE:
/* Switch to A-Device*/
if (test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "id\n");
phy->state = OTG_STATE_B_IDLE;
dotg->vbus_retry_count = 0;
work = 1;
} else {
phy->state = OTG_STATE_A_HOST;
ret = dwc3_otg_start_host(&dotg->otg, 1);
if ((ret == -EPROBE_DEFER) &&
dotg->vbus_retry_count < 3) {
/*
* Get regulator failed as regulator driver is
* not up yet. Will try to start host after 1sec
*/
phy->state = OTG_STATE_A_IDLE;
dev_dbg(phy->dev, "Unable to get vbus regulator. Retrying...\n");
delay = VBUS_REG_CHECK_DELAY;
work = 1;
dotg->vbus_retry_count++;
} else if (ret) {
/*
* Probably set_host was not called yet.
* We will re-try as soon as it will be called
*/
dev_dbg(phy->dev, "enter lpm as\n"
"unable to start A-device\n");
phy->state = OTG_STATE_A_IDLE;
pm_runtime_put_sync(phy->dev);
return;
}
}
break;
case OTG_STATE_A_HOST:
if (test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "id\n");
#ifdef CONFIG_PANTECH_SIO_BUG_FIX
/* FIXME : If OTG cable is disconnecting, below process is must completed
* before pm_runtime_suspend.
* So we are ignored pm_runtime_suspend request.
* LS4-USB tarial
*/
pm_runtime_get_noresume(phy->dev);
#endif
dwc3_otg_start_host(&dotg->otg, 0);
phy->state = OTG_STATE_B_IDLE;
dotg->vbus_retry_count = 0;
work = 1;
#ifdef CONFIG_PANTECH_SIO_BUG_FIX
pm_runtime_put_noidle(phy->dev);
#endif
}
break;
default:
dev_err(phy->dev, "%s: invalid otg-state\n", __func__);
}
if (work)
queue_delayed_work(system_nrt_wq, &dotg->sm_work, delay);
}
/**
* dwc3_otg_reset - reset dwc3 otg registers.
*
* @w: Pointer to the dwc3 otg workqueue
*/
static void dwc3_otg_reset(struct dwc3_otg *dotg)
{
static int once;
struct dwc3_ext_xceiv *ext_xceiv = dotg->ext_xceiv;
/*
* OCFG[2] - OTG-Version = 1
* OCFG[1] - HNPCap = 0
* OCFG[0] - SRPCap = 0
*/
if (ext_xceiv && !ext_xceiv->otg_capability)
dwc3_writel(dotg->regs, DWC3_OCFG, 0x4);
/*
* OCTL[6] - PeriMode = 1
* OCTL[5] - PrtPwrCtl = 0
* OCTL[4] - HNPReq = 0
* OCTL[3] - SesReq = 0
* OCTL[2] - TermSelDLPulse = 0
* OCTL[1] - DevSetHNPEn = 0
* OCTL[0] - HstSetHNPEn = 0
*/
if (!once) {
if (ext_xceiv && !ext_xceiv->otg_capability)
dwc3_writel(dotg->regs, DWC3_OCTL, 0x40);
once++;
}
/* Clear all otg events (interrupts) indications */
dwc3_writel(dotg->regs, DWC3_OEVT, 0xFFFF);
/* Enable ID/BSV StsChngEn event*/
if (ext_xceiv && !ext_xceiv->otg_capability)
dwc3_writel(dotg->regs, DWC3_OEVTEN,
DWC3_OEVTEN_OTGCONIDSTSCHNGEVNT |
DWC3_OEVTEN_OTGBDEVVBUSCHNGEVNT);
}
/**
* dwc3_otg_init - Initializes otg related registers
* @dwc: Pointer to out controller context structure
*
* Returns 0 on success otherwise negative errno.
*/
int dwc3_otg_init(struct dwc3 *dwc)
{
u32 reg;
int ret = 0;
struct dwc3_otg *dotg;
dev_dbg(dwc->dev, "dwc3_otg_init\n");
/*
* GHWPARAMS6[10] bit is SRPSupport.
* This bit also reflects DWC_USB3_EN_OTG
*/
reg = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
if (!(reg & DWC3_GHWPARAMS6_SRP_SUPPORT)) {
/*
* No OTG support in the HW core.
* We return 0 to indicate no error, since this is acceptable
* situation, just continue probe the dwc3 driver without otg.
*/
dev_dbg(dwc->dev, "dwc3_otg address space is not supported\n");
return 0;
}
/* Allocate and init otg instance */
dotg = kzalloc(sizeof(struct dwc3_otg), GFP_KERNEL);
if (!dotg) {
dev_err(dwc->dev, "unable to allocate dwc3_otg\n");
return -ENOMEM;
}
/* DWC3 has separate IRQ line for OTG events (ID/BSV etc.) */
dotg->irq = platform_get_irq_byname(to_platform_device(dwc->dev),
"otg_irq");
if (dotg->irq < 0) {
dev_err(dwc->dev, "%s: missing OTG IRQ\n", __func__);
ret = -ENODEV;
goto err1;
}
dotg->regs = dwc->regs;
dotg->otg.set_peripheral = dwc3_otg_set_peripheral;
dotg->otg.set_host = dwc3_otg_set_host;
/* This reference is used by dwc3 modules for checking otg existance */
dwc->dotg = dotg;
dotg->otg.phy = kzalloc(sizeof(struct usb_phy), GFP_KERNEL);
if (!dotg->otg.phy) {
dev_err(dwc->dev, "unable to allocate dwc3_otg.phy\n");
ret = -ENOMEM;
goto err1;
}
dotg->dwc = dwc;
dotg->otg.phy->otg = &dotg->otg;
dotg->otg.phy->dev = dwc->dev;
dotg->otg.phy->set_power = dwc3_otg_set_power;
dotg->otg.phy->set_suspend = dwc3_otg_set_suspend;
ret = usb_set_transceiver(dotg->otg.phy);
if (ret) {
dev_err(dotg->otg.phy->dev,
"%s: failed to set transceiver, already exists\n",
__func__);
goto err2;
}
dotg->otg.phy->state = OTG_STATE_UNDEFINED;
init_completion(&dotg->dwc3_xcvr_vbus_init);
INIT_DELAYED_WORK(&dotg->sm_work, dwc3_otg_sm_work);
ret = request_irq(dotg->irq, dwc3_otg_interrupt, IRQF_SHARED,
"dwc3_otg", dotg);
if (ret) {
dev_err(dotg->otg.phy->dev, "failed to request irq #%d --> %d\n",
dotg->irq, ret);
goto err3;
}
pm_runtime_get(dwc->dev);
return 0;
err3:
cancel_delayed_work_sync(&dotg->sm_work);
usb_set_transceiver(NULL);
err2:
kfree(dotg->otg.phy);
err1:
dwc->dotg = NULL;
kfree(dotg);
return ret;
}
/**
* dwc3_otg_sm_work - workqueue function.
*
* @w: Pointer to the dwc3 otg workqueue
*
* NOTE: After any change in phy->state,
* we must reschdule the state machine.
*/
static void dwc3_otg_sm_work(struct work_struct *w)
{
struct dwc3_otg *dotg = container_of(w, struct dwc3_otg, sm_work);
struct usb_phy *phy = dotg->otg.phy;
struct dwc3_charger *charger = dotg->charger;
bool work = 0;
dev_dbg(phy->dev, "%s state\n", otg_state_string(phy->state));
/* Check OTG state */
switch (phy->state) {
case OTG_STATE_UNDEFINED:
dwc3_otg_init_sm(dotg);
/* Switch to A or B-Device according to ID / BSV */
if (!test_bit(ID, &dotg->inputs) && phy->otg->host) {
dev_dbg(phy->dev, "!id\n");
phy->state = OTG_STATE_A_IDLE;
work = 1;
} else if (test_bit(B_SESS_VLD, &dotg->inputs)) {
dev_dbg(phy->dev, "b_sess_vld\n");
phy->state = OTG_STATE_B_IDLE;
work = 1;
} else {
phy->state = OTG_STATE_B_IDLE;
/* TODO: Enter low power state */
}
break;
case OTG_STATE_B_IDLE:
if (!test_bit(ID, &dotg->inputs) && phy->otg->host) {
dev_dbg(phy->dev, "!id\n");
phy->state = OTG_STATE_A_IDLE;
work = 1;
if (charger) {
if (charger->chg_type == DWC3_INVALID_CHARGER)
charger->start_detection(dotg->charger,
false);
else
charger->chg_type =
DWC3_INVALID_CHARGER;
}
} else if (test_bit(B_SESS_VLD, &dotg->inputs)) {
dev_dbg(phy->dev, "b_sess_vld\n");
if (charger) {
/* Has charger been detected? If no detect it */
switch (charger->chg_type) {
case DWC3_DCP_CHARGER:
/* TODO: initiate LPM */
break;
case DWC3_CDP_CHARGER:
dwc3_otg_start_peripheral(&dotg->otg,
1);
phy->state = OTG_STATE_B_PERIPHERAL;
work = 1;
break;
case DWC3_SDP_CHARGER:
dwc3_otg_start_peripheral(&dotg->otg,
1);
phy->state = OTG_STATE_B_PERIPHERAL;
work = 1;
break;
default:
dev_dbg(phy->dev, "chg_det started\n");
charger->start_detection(charger, true);
break;
}
} else {
/* no charger registered, start peripheral */
if (dwc3_otg_start_peripheral(&dotg->otg, 1)) {
/*
* Probably set_peripheral not called
* yet. We will re-try as soon as it
* will be called
*/
dev_err(phy->dev,
"unable to start B-device\n");
phy->state = OTG_STATE_UNDEFINED;
return;
}
}
} else {
if (charger) {
if (charger->chg_type == DWC3_INVALID_CHARGER)
charger->start_detection(dotg->charger,
false);
else
charger->chg_type =
DWC3_INVALID_CHARGER;
}
/* TODO: Enter low power state */
}
break;
case OTG_STATE_B_PERIPHERAL:
if (!test_bit(B_SESS_VLD, &dotg->inputs) ||
!test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "!id || !bsv\n");
dwc3_otg_start_peripheral(&dotg->otg, 0);
phy->state = OTG_STATE_B_IDLE;
if (charger)
charger->chg_type = DWC3_INVALID_CHARGER;
work = 1;
}
break;
case OTG_STATE_A_IDLE:
/* Switch to A-Device*/
if (test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "id\n");
phy->state = OTG_STATE_B_IDLE;
work = 1;
} else {
if (dwc3_otg_start_host(&dotg->otg, 1)) {
/*
* Probably set_host was not called yet.
* We will re-try as soon as it will be called
*/
dev_dbg(phy->dev,
"unable to start A-device\n");
phy->state = OTG_STATE_UNDEFINED;
return;
}
phy->state = OTG_STATE_A_HOST;
}
break;
case OTG_STATE_A_HOST:
if (test_bit(ID, &dotg->inputs)) {
dev_dbg(phy->dev, "id\n");
dwc3_otg_start_host(&dotg->otg, 0);
phy->state = OTG_STATE_B_IDLE;
work = 1;
}
break;
default:
dev_err(phy->dev, "%s: invalid otg-state\n", __func__);
}
if (work)
schedule_work(&dotg->sm_work);
}
static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
{
unsigned long flags;
irqreturn_t retval = IRQ_NONE;
struct musb *musb = __hci;
struct usb_otg *otg = musb->xceiv->otg;
void __iomem *tibase = musb->ctrl_base;
struct cppi *cppi;
u32 tmp;
spin_lock_irqsave(&musb->lock, flags);
cppi = container_of(musb->dma_controller, struct cppi, controller);
if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
retval = cppi_interrupt(irq, __hci);
tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
dev_dbg(musb->controller, "IRQ %08x\n", tmp);
musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
>> DAVINCI_USB_RXINT_SHIFT;
musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
>> DAVINCI_USB_TXINT_SHIFT;
musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
>> DAVINCI_USB_USBINT_SHIFT;
if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
void __iomem *mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
int err = musb->int_usb & MUSB_INTR_VBUSERROR;
err = is_host_enabled(musb)
&& (musb->int_usb & MUSB_INTR_VBUSERROR);
if (err) {
musb->int_usb &= ~MUSB_INTR_VBUSERROR;
musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
WARNING("VBUS error workaround (delay coming)\n");
} else if (is_host_enabled(musb) && drvvbus) {
MUSB_HST_MODE(musb);
otg->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
portstate(musb->port1_status |= USB_PORT_STAT_POWER);
del_timer(&otg_workaround);
} else {
musb->is_active = 0;
MUSB_DEV_MODE(musb);
otg->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
}
davinci_musb_source_power(musb, drvvbus, 0);
dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
devctl);
retval = IRQ_HANDLED;
}
if (musb->int_tx || musb->int_rx || musb->int_usb)
retval |= musb_interrupt(musb);
/* irq stays asserted until EOI is written */
musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
if (is_otg_enabled(musb)
&& musb->xceiv->state == OTG_STATE_B_IDLE)
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
spin_unlock_irqrestore(&musb->lock, flags);
return retval;
}
