int
omap_set_bus_speed(void *hdl, unsigned int speed, unsigned int *ospeed)
{
omap_dev_t *dev = hdl;
unsigned long iclk;
unsigned scll;
if (speed > 400000) {
errno = EINVAL;
return -1;
}
iclk = (speed>100000)?(OMAP_I2C_ICLK*3):(OMAP_I2C_ICLK);
/* OMAP_I2C_PSC is already set */
/* Set clock for "speed" bps */
scll = iclk/(speed << 1) - 7;
out16(dev->regbase + OMAP_I2C_SCLL, scll);
out16(dev->regbase + OMAP_I2C_SCLH, scll + 2);
if (ospeed)
*ospeed = iclk / ((scll + 7) << 1);
dev->speed = speed;
return 0;
}
bool RtlIsr(device_t *device, uint8_t irq)
{
rtl8139_t *rtl;
uint16_t status;
rtl = device->cookie;
SpinAcquire(&rtl->sem);
out16(rtl->iobase + IntrMask, 0);
status = in16(rtl->iobase + IntrStatus);
out16(rtl->iobase + IntrStatus, status & ~(RxFIFOOver | RxOverflow | RxOK));
if (status & (RxOK | RxErr))
RtlHandleRx(rtl);
else if (status & TxOK)
RtlHandleTx(rtl);
else
wprintf(L"rtl8139: unknown interrupt: isr = %04x\n", status);
out16(rtl->iobase + IntrStatus, status & (RxFIFOOver | RxOverflow | RxOK));
out16(rtl->iobase + IntrMask, IntrDefault);
SpinRelease(&rtl->sem);
return true;
}
int
omap_set_bus_speed(void *hdl, unsigned int speed, unsigned int *ospeed)
{
omap_dev_t *dev = hdl;
unsigned long iclk;
unsigned scll;
if (speed > 400000) {
errno = EINVAL;
return -1;
}
iclk = OMAP_I2C_ICLK;
/* OMAP_I2C_PSC is already set */
/* Set clock for "speed" bps */
scll = iclk/(speed << 1) - 7;
out16(dev->regbase + OMAP_I2C_SCLL, scll);
out16(dev->regbase + OMAP_I2C_SCLH, scll + 2);
if (ospeed)
*ospeed = iclk / ((scll + 7) << 1);
dev->speed = speed;
//fprintf(stderr, "omap_i2c_set_bus_speed: speed=%d ospeed=%d iclk=%d scll=%d\n", speed, iclk / ((scll + 7) << 1), iclk, scll);
return 0;
}
/*
* write block to memory card
* utilize basic DMA (known as SDMA in documents)
* processor will spin to wait.
*
* pa = physical address
* count = block count
* offset = starting offset on card.
*
**********************************************
* WARNING: OFFSET IS IN BYTES ON SD(SC) CARD *
* BUT IN 512-BYTE BLOCKS ON SDHC CARD! *
**********************************************
*
* To make cross-platform design easier, we allow 512-byte blocks only.
*
* return values:
* 0 = good
* -1 = no card
* -2 = error sending CMD25
* -3 = error during DMA transfer
*/
int sd_dma_spin_write(u32 pa, u16 count, u32 offset)
{
int ret;
u16 state16;
u32 state32;
/* check card */
state32 = in32(SD_BASE + SD_PRES_STATE_OFFSET);
if (!(state32 & SD_PSR_CARD_INSRT)) return -1;
/* block size set to 512 during controller init, skipping check */
/* write address */
out32(SD_BASE + SD_SDMA_SYS_ADDR_OFFSET, pa);
/* CMD18 with auto_cmd12 */
ret = sd_spin_send_cmd(SD_CMD25, count, offset, 2);
if (ret) return -2;
/* wait for transfer complete */
do {
state16 = in16(SD_BASE + SD_NORM_INTR_STS_OFFSET);
if (state16 & SD_INTR_ERR) {
out16(SD_BASE + SD_ERR_INTR_STS_OFFSET, \
SD_ERR_INTR_ALL);
return -3;
}
} while (!(state16 & SD_INTR_TC));
/* clean up */
out16(SD_BASE + SD_NORM_INTR_STS_OFFSET, SD_INTR_TC);
return 0;
}
int r6040_open(struct net_device *dev) {
#if INTERRUPTS_ENABLE
if (-1 == irq_attach(0x0a, irq_handler, 0, dev, "RDC r6040")) {
return -1;
}
out16(0, MT_ICR);
out16(0, MR_ICR);
out16(INT_MASK, MIER);
#endif
return 0;
}
void
omap_fini(void *hdl)
{
omap_dev_t *dev = hdl;
out16(dev->regbase + OMAP_I2C_CON, 0);
out16(dev->regbase + OMAP_I2C_IE, 0);
InterruptDetach(dev->iid);
ConnectDetach(dev->coid);
ChannelDestroy(dev->chid);
munmap_device_io (dev->regbase, dev->reglen);
free (hdl);
}
ACPI_STATUS
AcpiOsWritePort (
ACPI_IO_ADDRESS Address,
UINT32 Value,
UINT32 Width)
{
switch (Width) {
case 8:
out8(Address, Value);
break;
case 16:
out16(Address,Value);
break;
case 32:
out32(Address,Value);
break;
default:
return (AE_ERROR);
}
// dbgprintf("%s %x, %x\n",__FUNCTION__, Address, Value);
return (AE_OK);
};
ACPI_STATUS AcpiOsWritePort(
ACPI_IO_ADDRESS Address,
UINT32 Value,
UINT32 Width) {
PRINTD("AcpiOsWritePort() called");
switch (Width) {
case 8: {
out8((uint8_t) Value, Address);
break;
}
case 16: {
out16((uint16_t) Value, Address);
break;
}
case 32: {
out32(Value, Address);
break;
}
default: {
return AE_BAD_PARAMETER;
}
}
return AE_OK;
}
static status_t
pci_mech1_write_config(void *cookie, uint8 bus, uint8 device, uint8 function,
uint8 offset, uint8 size, uint32 value)
{
cpu_status cpu;
status_t status = B_OK;
PCI_LOCK_CONFIG(cpu);
out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT);
switch (size) {
case 1:
out8(value, PCI_MECH1_DATA_PORT + (offset & 3));
break;
case 2:
out16(value, PCI_MECH1_DATA_PORT + (offset & 3));
break;
case 4:
out32(value, PCI_MECH1_DATA_PORT);
break;
default:
status = B_ERROR;
break;
}
PCI_UNLOCK_CONFIG(cpu);
return status;
}
static int write_register16(void *cookie,int reg,uint16 value)
{
pci_bus_cookie *bus_cookie = cookie;
uint16 reg_addr = bus_cookie->pio_reg_addrs[reg];
out16(value,reg_addr);
return 0;
}
static status_t
pci_mech2_write_config(void *cookie, uint8 bus, uint8 device, uint8 function,
uint8 offset, uint8 size, uint32 value)
{
cpu_status cpu;
status_t status = B_OK;
PCI_LOCK_CONFIG(cpu);
out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT);
out8(bus, PCI_MECH2_FORWARD_PORT);
switch (size) {
case 1:
out8(value, PCI_MECH2_CONFIG_PORT(device, offset));
break;
case 2:
out16(value, PCI_MECH2_CONFIG_PORT(device, offset));
break;
case 4:
out32(value, PCI_MECH2_CONFIG_PORT(device, offset));
break;
default:
status = B_ERROR;
break;
}
out8(0, PCI_MECH2_ENABLE_PORT);
PCI_UNLOCK_CONFIG(cpu);
return status;
}
uint32_t pci_write_config16(uint32_t bus, uint32_t dev_fn,
uint32_t where, uint16_t value) {
out32(PCI_CONFIG_CMD(bus, dev_fn, where), PCI_CONFIG_ADDRESS);
/* Change the selection bits in a double word from 2nd to 1st */
out16(value, PCI_CONFIG_DATA + (where & 2));
return PCIUTILS_SUCCESS;
}
void fpga_init(void)
{
/*
* by default sdram access is disabled by fpga
*/
out16(FPGA_REG10, (in16 (FPGA_REG10) |
FPGA_REG10_SDRAM_ENABLE |
FPGA_REG10_ENABLE_DISPLAY ));
return;
}
void RtlHandleRx(rtl8139_t *rtl)
{
uint32_t ring_offs, rx_size, rx_status;
rxpacket_t *packet;
ring_offs = rtl->cur_rx % RX_BUF_LEN;
rx_status = *(uint32_t*) (rtl->rx_ring + ring_offs);
rx_size = rx_status >> 16;
rx_status &= 0xffff;
if ((rx_status & (RxBadSymbol | RxRunt | RxTooLong | RxCRCErr | RxBadAlign)) ||
(rx_size < ETH_ZLEN) ||
(rx_size > ETH_FRAME_LEN + 4))
{
wprintf(L"rx error 0x%x\n", rx_status);
RtlReset(rtl); /* this clears all interrupts still pending */
RtlStartIo(rtl);
return;
}
packet = malloc(sizeof(rxpacket_t) - 1 + rx_size - 4);
if (packet == NULL)
return;
packet->length = rx_size - 4; /* no one cares about the FCS */
/* Received a good packet */
if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN)
{
int semi_count = RX_BUF_LEN - ring_offs - 4;
memcpy(packet->data, rtl->rx_ring + ring_offs + 4, semi_count);
memcpy(packet->data + semi_count, rtl->rx_ring, rx_size - 4 - semi_count);
//wprintf(L"rx packet %d+%d bytes", semi_count,rx_size - 4 - semi_count);
}
else
{
memcpy(packet->data, rtl->rx_ring + ring_offs + 4, packet->length);
//wprintf(L"rx packet %d bytes", rx_size-4);
}
/*wprintf(L" at %X type %02X%02X rxstatus %hX\n",
(unsigned long)(rtl->rx_ring + ring_offs+4),
packet->data[12], packet->data[13], rx_status);*/
packet->type = *(unsigned short*) (packet->data + 12);
LIST_ADD(rtl->packet, packet);
rtl->cur_rx = (rtl->cur_rx + rx_size + 4 + 3) & ~3;
out16(rtl->iobase + RxBufPtr, rtl->cur_rx - 16);
RtlStartIo(rtl);
}
/* The RDC interrupt handler */
static irq_return_t irq_handler(unsigned int irq_num, void *dev_id) {
uint16_t misr, status;
printk("IRQ!\n");
/* Save MIER */
misr = in16(MIER);
/* Mask off RDC MAC interrupt */
out16(MSK_INT, MIER);
/* Read MISR status and clear */
status = in16(MISR);
if (status == 0x0000 || status == 0xffff) {
/* Restore RDC MAC interrupt */
out16(misr, MIER);
return IRQ_NONE;
}
//TODO:
/* Restore RDC MAC interrupt */
out16(misr, MIER);
return IRQ_HANDLED;
}
int misc_init_f (void)
{
uint reg;
out16(FPGA_REG10, (in16(FPGA_REG10) &
~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
FPGA_REG10_10MHZ_ENABLE |
FPGA_REG10_100MHZ_ENABLE |
FPGA_REG10_GIGABIT_ENABLE |
FPGA_REG10_FULL_DUPLEX );
udelay(10000); /* wait 10ms */
out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
/* minimal init for PCIe */
/* pci express 0 Endpoint Mode */
mfsdr(SDRN_PESDR_DLPSET(0), reg);
reg &= (~0x00400000);
mtsdr(SDRN_PESDR_DLPSET(0), reg);
/* pci express 1 Rootpoint Mode */
mfsdr(SDRN_PESDR_DLPSET(1), reg);
reg |= 0x00400000;
mtsdr(SDRN_PESDR_DLPSET(1), reg);
/* pci express 2 Rootpoint Mode */
mfsdr(SDRN_PESDR_DLPSET(2), reg);
reg |= 0x00400000;
mtsdr(SDRN_PESDR_DLPSET(2), reg);
out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
~FPGA_REG1C_PE0_ROOTPOINT &
~FPGA_REG1C_PE1_ENDPOINT &
~FPGA_REG1C_PE2_ENDPOINT));
return 0;
}
void RtlReset(rtl8139_t *rtl)
{
unsigned i;
out(rtl->iobase + ChipCmd, CmdReset);
rtl->cur_rx = 0;
rtl->cur_tx = 0;
/* Give the chip 10ms to finish the reset. */
i = WrapSysUpTime() + 10;
while ((in(rtl->iobase + ChipCmd) & CmdReset) != 0 &&
WrapSysUpTime() < i)
/* wait */;
for (i = 0; i < _countof(rtl->station_address); i++)
out(rtl->iobase + MAC0 + i, rtl->station_address[i]);
/* Must enable Tx/Rx before setting transfer thresholds! */
out(rtl->iobase + ChipCmd, CmdRxEnb | CmdTxEnb);
out32(rtl->iobase + RxConfig,
(RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8)); /* accept no frames yet! */
out32(rtl->iobase + TxConfig, (TX_DMA_BURST<<8)|0x03000000);
/* The Linux driver changes Config1 here to use a different LED pattern
* for half duplex or full/autodetect duplex (for full/autodetect, the
* outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
* TX/RX, Link100, Link10). This is messy, because it doesn't match
* the inscription on the mounting bracket. It should not be changed
* from the configuration EEPROM default, because the card manufacturer
* should have set that to match the card. */
out32(rtl->iobase + RxBuf, rtl->rx_phys);
/* Start the chip's Tx and Rx process. */
out32(rtl->iobase + RxMissed, 0);
/* set_rx_mode */
out(rtl->iobase + RxConfig, AcceptBroadcast|AcceptMyPhys);
/* If we add multicast support, the MAR0 register would have to be
* initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
* only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
out(rtl->iobase + ChipCmd, CmdRxEnb | CmdTxEnb);
/* Disable all known interrupts by setting the interrupt mask. */
//out16(rtl->iobase + IntrMask, 0);
out16(rtl->iobase + IntrMask, IntrDefault);
}
int
omap_set_bus_speed(void *hdl, unsigned int speed, unsigned int *ospeed)
{
omap_dev_t *dev = hdl;
unsigned long iclk;
unsigned scll;
/* This driver support bus speed range from 8KHz to 400KHz
* limit the low bus speed to 8KHz to protect SCLL/SCLH from overflow(large than 0xff)
* if speed=8KHz, iclk=4MHz, then SCLL=0xf3, SCLH=0xf5
*/
if (speed > 400000 || speed < 8000) {
fprintf(stderr, "i2c-omap35xx: Invalid bus speed(%d)\n", speed);
errno = EINVAL;
return -1;
}
/* Set the I2C prescaler register to obtain the maximum I2C bit rates
* and the maximum period of the filtered spikes in F/S mode:
* Stander Mode: I2Ci_INTERNAL_CLK = 4 MHz
* Fast Mode: I2Ci_INTERNAL_CLK = 9.6 MHz
*/
#if defined(VARIANT_j5)
if (speed <= 100000) {
out16(dev->regbase + OMAP_I2C_PSC, 11); // I2Ci_INTERNAL_CLK = 4 MHz
iclk = OMAP_I2C_ICLK;
} else {
out16(dev->regbase + OMAP_I2C_PSC, 4); // I2Ci_INTERNAL_CLK = 9.6 MHz
iclk = OMAP_I2C_ICLK_9600K;
}
#else
if (speed <= 100000) {
out16(dev->regbase + OMAP_I2C_PSC, 23); // I2Ci_INTERNAL_CLK = 4 MHz
iclk = OMAP_I2C_ICLK;
} else {
out16(dev->regbase + OMAP_I2C_PSC, 9); // I2Ci_INTERNAL_CLK = 9.6 MHz
iclk = OMAP_I2C_ICLK_9600K;
}
#endif
/* OMAP_I2C_PSC is already set */
/* Set clock for "speed" bps */
scll = iclk/(speed << 1) - 7;
out16(dev->regbase + OMAP_I2C_SCLL, scll);
out16(dev->regbase + OMAP_I2C_SCLH, scll + 2);
dev->speed = iclk / ((scll + 7) << 1);
if (ospeed)
*ospeed = dev->speed;
return 0;
}
/*
* send non-data command
* data commands are a little different, use read/write instead.
*
* 0 = good
* -1 = command inhibited
* -2 = command has data but data is inhibited
* -3 = controller reported error
*/
int sd_spin_send_cmd(u16 cmd, u16 count, u32 arg, int mode)
{
u32 state;
u16 result, tmp16;
/* frame the command */
cmd = sd_frame_cmd(cmd);
/* do a state check */
state = in32(SD_BASE + SD_PRES_STATE_OFFSET);
if (state & SD_PSR_INHIBIT_CMD) return -1;
if ((state & SD_PSR_INHIBIT_DAT) && (cmd & SD_DAT_PRESENT)) return -2;
/* write block count */
out16(SD_BASE + SD_BLK_CNT_OFFSET, count);
out16(SD_BASE + SD_TIMEOUT_CTRL_OFFSET, 0xE);
/* write argument */
out32(SD_BASE + SD_ARGMT_OFFSET, arg);
out16(SD_BASE + SD_NORM_INTR_STS_OFFSET, SD_NORM_INTR_ALL);
out16(SD_BASE + SD_ERR_INTR_STS_OFFSET, SD_ERR_INTR_ALL);
/* set transfer mode */
switch(mode) {
/* DMA read */
case 1:
tmp16 = SD_TM_MUL_SIN_BLK_SEL | SD_TM_DAT_DIR_SEL | \
SD_TM_AUTO_CMD12_EN | SD_TM_BLK_CNT_EN | \
SD_TM_DMA_EN;
break;
/* DMA write */
case 2:
tmp16 = SD_TM_MUL_SIN_BLK_SEL | SD_TM_AUTO_CMD12_EN | \
SD_TM_BLK_CNT_EN | SD_TM_DMA_EN;
break;
/* non-data */
default:
tmp16 = SD_TM_DMA_EN;
break;
}
out16(SD_BASE + SD_XFER_MODE_OFFSET, tmp16);
/* write command */
out16(SD_BASE + SD_CMD_OFFSET, cmd);
/* wait for result */
do {
result = in16(SD_BASE + SD_NORM_INTR_STS_OFFSET);
if (result & SD_INTR_ERR) return -3;
/* We don't read error states, and we dont't clear them. */
} while(!(result & SD_INTR_CC));
/* Clear */
out16(SD_BASE + SD_NORM_INTR_STS_OFFSET, SD_INTR_CC);
return 0;
}
static int __write_sectors_lba48(const void *data, unsigned long long sector,
size_t count)
{
const unsigned long slo = sector & 0xfffffffful;
const unsigned long shi = sector >> 32;
const unsigned clo = count & 0xffu;
const unsigned chi = count >> 8;
out8(IDE_DEVCTL_REG, IDE_NIEN);
out8(IDE_SC_REG, chi);
out8(IDE_LBA0_REG, shi & 0xff);
out8(IDE_LBA1_REG, (shi >> 8) & 0xff);
out8(IDE_LBA2_REG, (shi >> 16) & 0xff);
out8(IDE_SC_REG, clo);
out8(IDE_LBA0_REG, slo & 0xff);
out8(IDE_LBA1_REG, (slo >> 8) & 0xff);
out8(IDE_LBA2_REG, (slo >> 16) & 0xff);
out8(IDE_DEV_REG, IDE_LBA);
out8(IDE_CMD_REG, IDE_CMD_WRITE_LBA48);
ide_wait_ready();
const uint16_t *wptr = (uint16_t *)data;
const size_t words = IDE_SECTOR_SIZE / sizeof(*wptr);
for (size_t i = 0; i != count; ++i) {
for (size_t j = 0; j != words; ++j)
out16(IDE_DATA_REG, *wptr++);
in8(IDE_ASTATUS_REG); // wait one PIO transfer cycle
if (ide_wait_ready() != 0)
return -1;
}
return 0;
}
/*
* Initialize the controller.
* This can (almost) only be done in polling mode.
*/
void sd_init()
{
u16 tmp16;
u8 tmp8;
/* reset */
out8(SD_BASE + SD_SW_RST_OFFSET, SD_SWRST_ALL_MASK);
while (in8(SD_BASE + SD_SW_RST_OFFSET) & SD_SWRST_ALL_MASK);
/* capabilities = in32(SD_BASE + SD_CAPS_OFFSET) */
/* enable internal clock */
tmp16 = SD_CC_SDCLK_FREQ_D128 | SD_CC_INT_CLK_EN;
out16(SD_BASE + SD_CLK_CTRL_OFFSET, tmp16);
while (!(in16(SD_BASE + SD_CLK_CTRL_OFFSET) & SD_CC_INT_CLK_STABLE));
/* enable SD clock */
tmp16 = in16(SD_BASE + SD_CLK_CTRL_OFFSET) | SD_CC_SD_CLK_EN;
out16(SD_BASE + SD_CLK_CTRL_OFFSET, tmp16);
/* enable bus power */
tmp8 = SD_PC_BUS_VSEL_3V3 | SD_PC_BUS_PWR;
out8(SD_BASE + SD_POWER_CTRL_OFFSET, tmp8);
out8(SD_BASE + SD_HOST_CTRL1_OFFSET, SD_HC_DMA_SDMA);
/*
* Xilinx's driver uses ADMA2 by default, we use single-operation
* DMA to avoid putting descriptors in memory.
*/
/* enable interrupt status except card */
tmp16 = SD_NORM_INTR_ALL & (~SD_INTR_CARD);
out16(SD_BASE + SD_NORM_INTR_STS_EN_OFFSET, tmp16);
out16(SD_BASE + SD_ERR_INTR_STS_EN_OFFSET, SD_ERR_INTR_ALL);
/* but disable all interrupt signals */
out16(SD_BASE + SD_NORM_INTR_SIG_EN_OFFSET, 0x0);
out16(SD_BASE + SD_ERR_INTR_SIG_EN_OFFSET, 0x0);
/* set block size to 512 */
out16(SD_BASE + SD_BLK_SIZE_OFFSET, 512);
}
/*
* hcu_led_set value to be placed into the LEDs (max 6 bit)
*/
void hcu_led_set(u32 value)
{
out16(SYS_IO_ADDRESS, value);
}
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
char *env;
unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for yucca card presence */
if (!yucca_pcie_card_present(i))
continue;
#ifdef PCIE_ENDPOINT
yucca_setup_pcie_fpga_endpoint(i);
if (ppc440spe_init_pcie_endport(i)) {
#else
yucca_setup_pcie_fpga_rootpoint(i);
if (ppc440spe_init_pcie_rootport(i)) {
#endif
printf("PCIE%d: initialization failed\n", i);
continue;
}
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
PCI_REGION_MEM
);
hose->region_count = 1;
pci_register_hose(hose);
#ifdef PCIE_ENDPOINT
ppc440spe_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul (env, NULL, 10);
if (delay > 5)
printf ("Warning, expect noticable delay before PCIe"
"scan due to 'pciscandelay' value!\n");
mdelay (delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
#endif
}
}
#endif /* defined(CONFIG_PCI) */
int misc_init_f (void)
{
uint reg;
#if defined(CONFIG_STRESS)
uint i ;
uint disp;
#endif
out16(FPGA_REG10, (in16(FPGA_REG10) &
~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
FPGA_REG10_10MHZ_ENABLE |
FPGA_REG10_100MHZ_ENABLE |
FPGA_REG10_GIGABIT_ENABLE |
FPGA_REG10_FULL_DUPLEX );
udelay(10000); /* wait 10ms */
out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
/* minimal init for PCIe */
/* pci express 0 Endpoint Mode */
mfsdr(SDR0_PE0DLPSET, reg);
reg &= (~0x00400000);
mtsdr(SDR0_PE0DLPSET, reg);
/* pci express 1 Rootpoint Mode */
mfsdr(SDR0_PE1DLPSET, reg);
reg |= 0x00400000;
mtsdr(SDR0_PE1DLPSET, reg);
/* pci express 2 Rootpoint Mode */
mfsdr(SDR0_PE2DLPSET, reg);
reg |= 0x00400000;
mtsdr(SDR0_PE2DLPSET, reg);
out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
~FPGA_REG1C_PE0_ROOTPOINT &
~FPGA_REG1C_PE1_ENDPOINT &
~FPGA_REG1C_PE2_ENDPOINT));
#if defined(CONFIG_STRESS)
/*
* all this setting done by linux only needed by stress an charac. test
* procedure
* PCIe 1 Rootpoint PCIe2 Endpoint
* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 8; i++, disp += 3) {
mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
}
/*
* PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 4; i++, disp += 3) {
mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
}
/*
* PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 4; i++, disp += 3) {
mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
}
reg = 0x21242222;
mtsdr(SDR0_PE2UTLSET1, reg);
reg = 0x11000000;
mtsdr(SDR0_PE2UTLSET2, reg);
/* pci express 1 Endpoint Mode */
reg = 0x00004000;
mtsdr(SDR0_PE2DLPSET, reg);
mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
#endif
return 0;
}
/**
* @brief chek_advance
* @param host struct uhci_host
*/
int
uhci_check_advance(struct usb_host *usbhc)
{
struct uhci_host *host = (struct uhci_host *)usbhc->private;
struct usb_request_block *urb, *nexturb;
int advance = 0;
int ucfn = -1;
if (cmpxchgl(&host->incheck, 0U, 1U))
return 0;
#if 0
in16(host->iobase + UHCI_REG_USBSTS, &usbsts);
if (usbsts)
dprintft(2, "%04x: %s: usbsts = %04x\n",
host->iobase, __FUNCTION__, usbsts);
#endif /* 0 */
spinlock_lock(&host->lock_hfl);
recheck:
for (urb = LIST4_HEAD (host->inproc_urbs, list); urb;
urb = nexturb) {
urb->prevent_del = true;
spinlock_unlock(&host->lock_hfl);
/* update urb->status */
if (urb->status == URB_STATUS_RUN) {
if (ucfn < 0)
ucfn = uhci_current_frame_number (host);
uhci_check_urb_advance_sub (host, ucfn, host->hc, urb);
}
switch (urb->status) {
default: /* errors */
dprintft(2, "%04x: %s: got some errors(%s) "
"for urb(%p).\n", host->iobase,
__FUNCTION__,
uhci_error_status_string(urb->status), urb);
/* through */
case URB_STATUS_ADVANCED:
if (urb->callback)
(urb->callback) (host->hc, urb, urb->cb_arg);
advance++;
break;
case URB_STATUS_NAK:
dprintft(2, "%04x: %s: got an NAK for urb(%p).\n",
host->iobase, __FUNCTION__, urb);
urb->status = URB_STATUS_RUN;
case URB_STATUS_RUN:
case URB_STATUS_FINALIZED:
case URB_STATUS_UNLINKED:
break;
}
spinlock_lock(&host->lock_hfl);
nexturb = LIST4_NEXT (urb, list);
urb->prevent_del = false;
if (urb->deferred_del) {
urb->deferred_del = false;
spinlock_unlock(&host->lock_hfl);
uhci_deactivate_urb(host->hc, urb);
spinlock_lock(&host->lock_hfl);
goto recheck;
}
}
spinlock_unlock(&host->lock_hfl);
#if 0
if (advance) {
dprintft(3, "%s: USBSTS register cleared.\n",
__FUNCTION__);
out16(host->iobase + UHCI_REG_USBSTS, usbsts);
}
#endif
host->incheck = 0U;
return advance;
}
/**
* @brief chek_advance
* @param host struct uhci_host
*/
int
check_advance(struct uhci_host *host)
{
struct usb_request_block *urb, *nexturb;
int advance = 0, ret = 0;
u16 usbsts = 0U;
if (cmpxchgl(&host->incheck, 0U, 1U))
return 0;
#if 0
in16(host->iobase + UHCI_REG_USBSTS, &usbsts);
if (usbsts)
dprintft(2, "%04x: %s: usbsts = %04x\n",
host->iobase, __FUNCTION__, usbsts);
#endif /* 0 */
urb = host->inproc_urbs;
while (urb) {
/* update urb->status */
if (urb->status == URB_STATUS_RUN)
check_urb_advance(host, urb, usbsts);
switch (urb->status) {
case URB_STATUS_UNLINKED:
spinlock_lock(&host->lock_hfl);
nexturb = urb->next;
remove_urb(&host->inproc_urbs, urb);
destroy_urb(host, urb);
dprintft(3, "%04x: %s: urb(%p) destroyed.\n",
host->iobase, __FUNCTION__, urb);
urb = nexturb;
spinlock_unlock(&host->lock_hfl);
continue;
default: /* errors */
dprintft(2, "%04x: %s: got some errors(%s) "
"for urb(%p).\n", host->iobase,
__FUNCTION__,
uhci_error_status_string(urb->status), urb);
uhci_dump_all(3, host, urb);
/* through */
case URB_STATUS_ADVANCED:
if (urb->callback)
ret = (urb->callback)(host->hc, urb,
urb->cb_arg);
advance++;
break;
case URB_STATUS_NAK:
dprintft(2, "%04x: %s: got an NAK for urb(%p).\n",
host->iobase, __FUNCTION__, urb);
if (urb->shadow)
uhci_force_copyback(host, urb);
urb->status = URB_STATUS_RUN;
case URB_STATUS_RUN:
case URB_STATUS_FINALIZED:
break;
}
urb = urb->next;
}
#if 0
if (advance) {
dprintft(3, "%s: USBSTS register cleared.\n",
__FUNCTION__);
out16(host->iobase + UHCI_REG_USBSTS, usbsts);
}
#endif
host->incheck = 0U;
return advance;
}
static void r6040_set_rx_start(eth_desc_t* desc) {
unsigned long tmp = (unsigned long) desc;
out16((tmp & 0xffff), RX_START_LOW);
tmp >>= 16;
out16((tmp & 0xffff), RX_START_HIGH);
}
void
arch_isa_write_io_16(int mapped_io_addr, uint16 value)
{
out16(value, mapped_io_addr);
}
// ------------------------------------------------------------------------------------------------
void pci_out16(uint id, uint reg, u16 data)
{
u32 address = 0x80000000 | id | (reg & 0xfc);
out32(PCI_CONFIG_ADDR, address);
out16(PCI_CONFIG_DATA + (reg & 0x02), data);
}
void r6040_rx_enable(void) {
unsigned short tmp = in16(MCR0);
out16(tmp | (1 << 1), MCR0);
// out16(2, MCR0);
}
char *
hex2mem(char *buf, char *mem, int count) {
int i;
unsigned char ch;
char *out;
int special;
union {
uint8_t u8;
uint16_t u16;
uint32_t u32;
} temp;
// Handle 1/2/4 bytes writes specially - they might be "out8/16/32"
// requests, or we might be talking to a mem mapped register that
// doesn't like taking information one byte at a time.
special = 0;
out = mem;
if(cpu_handle_alignment(mem, count)) {
switch(count) {
case 1:
case 2:
case 4:
special = 1;
out = (void *)&temp;
break;
default:
break;
}
}
for(i=0;i<count;i++) {
ch = chartohex(*buf++) << 4;
ch = ch + chartohex(*buf++);
*out++ = ch;
}
if(special) {
switch(count) {
case 1:
if(MAP_IN_RANGE(inout, mem)) {
out8(MAP_OFFSET(inout, mem), temp.u8);
} else {
*(uint8_t *)mem = temp.u8;
}
break;
case 2:
if(MAP_IN_RANGE(inout, mem)) {
out16(MAP_OFFSET(inout, mem), temp.u16);
} else {
*(uint16_t *)mem = temp.u16;
}
break;
case 4:
if(MAP_IN_RANGE(inout, mem)) {
out32(MAP_OFFSET(inout, mem), temp.u32);
} else {
*(uint32_t *)mem = temp.u32;
}
break;
default:
break;
}
}
return(mem + count);
}
